A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.

A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.

A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.