A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

A semiconductor device includes a high-voltage semiconductor transistor chip having a front side and a backside. A low-voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further includes a dielectric inorganic substrate having a first side and a second side opposite the first side. A pattern of first metal structures runs through the dielectric inorganic substrate and is connected to the low-voltage load electrode. At least one second metal structure runs through the dielectric inorganic substrate and is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 μm.

A semiconductor device includes a high-voltage semiconductor transistor chip having a front side and a backside. A low-voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further includes a dielectric inorganic substrate having a first side and a second side opposite the first side. A pattern of first metal structures runs through the dielectric inorganic substrate and is connected to the low-voltage load electrode. At least one second metal structure runs through the dielectric inorganic substrate and is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 μm.

A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1.sup.st cell and a 2.sup.nd cell placed next to each other in a cell width direction, wherein the 1.sup.st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1.sup.st cell, and connects a vertical field-effect transistor (VFET) of the 1.sup.st cell to a power rail of the 1.sup.st cell, wherein a 2.sup.nd cell includes a connector connected to a power rail of the 2.sup.nd cell, wherein the fin of the 1.sup.st cell and the connector of the 2.sup.nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1.sup.st cell and the connector of the 2.sup.nd cell are merged.

A semiconductor device includes a stacked structure with first conductive layers and insulating layers that are stacked alternately with each other, second conductive layers located on the stacked structure, first openings passing through the second conductive layers and the stacked structure and having a first width, second conductive patterns formed in the first openings and located on the stacked structure to be electrically coupled to the second conductive layers, data storage patterns formed in the first openings and located under the second conductive patterns, and channel layers formed in the data storage patterns and the second conductive patterns.

A semiconductor substrate (1) includes a front surface and a back surface opposite to each other, and a through-hole (9) penetrating from the back surface to the front surface. A metal film (10) surrounding the through-hole (9) is formed in a ring shape on the front surface. A front-surface electrode (6) includes a wiring electrode (11,12) covering the through-hole (9) and the metal film (10) and is joined to the front surface outside the metal film (10). A back-surface electrode (15) is formed on the back surface and inside the through-hole (9) and connected to the wiring electrode (11,12). The metal film (10) has a lower ionization tendency and a higher work function than the wiring electrode (11,12).

A semiconductor substrate (1) includes a front surface and a back surface opposite to each other, and a through-hole (9) penetrating from the back surface to the front surface. A metal film (10) surrounding the through-hole (9) is formed in a ring shape on the front surface. A front-surface electrode (6) includes a wiring electrode (11,12) covering the through-hole (9) and the metal film (10) and is joined to the front surface outside the metal film (10). A back-surface electrode (15) is formed on the back surface and inside the through-hole (9) and connected to the wiring electrode (11,12). The metal film (10) has a lower ionization tendency and a higher work function than the wiring electrode (11,12).

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

A semiconductor device includes a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate. The at least one interface region includes a first portion of the semiconductor substrate, a first portion of the metal nitride layer, and an interface between the first portion of the semiconductor substrate and the first portion of the metal nitride layer. A concentration of nitrogen content at the first portion of the metal nitride layer is higher than a concentration of nitrogen content at a second portion, of the metal nitride layer, outside the interface region. A distribution of nitrogen content throughout the metal nitride layer may have a maximum concentration at the first portion of the metal nitride layer. Alternatively and/or additionally, a method for producing such a semiconductor device is provided herein.

A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.