A method of forming a semiconductor device includes: forming a dummy gate structure over a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack over the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings exposes first portions of the first semiconductor material and second portions of the second semiconductor material; recessing the exposed first portions of the first semiconductor material to form sidewall recesses in the first semiconductor material; lining the sidewall recesses with a first dielectric material; depositing a second dielectric material in the sidewall recesses on the first dielectric material; after depositing the second dielectric material, annealing the second dielectric material; and after the annealing, forming source/drain regions in the openings.

A semiconductor device includes an active area extending in a first direction over a substrate, the active area including at least one conductive path extending from a source region, through a channel region, to a drain region; and a gate dielectric on a surface of the at least one conductive path in the channel region. The semiconductor device also includes an isolating fin at a first side of the active area, the isolating fin having a first fin region having a first fin width adjacent to the source region, a second fin region having a second fin width adjacent to the channel region, and a third fin region having the first fin width adjacent to the drain region; and a gate electrode against the gate dielectric in the channel region.

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second oxidation stop layers on the n- and p-type S/D regions, respectively, epitaxially growing first and second semiconductor layers on the first and second oxidation stop layers, respectively, converting the first and second semiconductor layers into first and second semiconductor oxide layers, respectively, forming a first silicide-germanide layer on the p-type S/D region, and forming a second silicide-germanide layer on the first silicide-germanide layer and on the n-type S/D region.

A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

Integrated circuit (IC) chips are provided. An IC chip according to the present corner area between an outer corner of the device region and an inner corner of the ring region. The ring region includes a first active region extending along a first direction, a first source/drain contact disposed partially over the first active region and extending along the first direction, and first gate structures disposed completely over the first active region and each extending lengthwise along the first direction. The corner area includes a second active region extending along a second direction that forms an acute angle with the first direction, a second source/drain contact disposed partially over the second active region and extending along the second direction, and second gate structures disposed over the second active region and each extending along the first direction.

A field effect transistor includes a semiconductor substrate and multiple trenches disposed at a top surface of the semiconductor substrate. The trenches extend in a first direction at the top surface of the semiconductor substrate, and are disposed to be spaced apart in a direction perpendicular to the first direction. Connection regions are disposed below body regions. The connection regions extend in a second direction intersecting the first direction in a top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the second direction. Field relaxation regions are disposed below the connection regions and the trenches. The field relaxation regions extend in a third direction intersecting the first direction and the second direction in the top view of the semiconductor substrate, and are spaced apart in a direction perpendicular to the third direction.

A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

A device includes a substrate including an active region, a gate stack over the active region, and a hard mask over the gate stack. The hard mask includes a capping layer, a buttress layer extending along sidewalls and a bottom of the capping layer, and a liner layer extending along sidewalls and a bottom of the buttress layer. The buttress layer includes a metal oxide material or a metal nitride material.

A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.

A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.