A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.

A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.

A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.

Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.