Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a barrier layer, a third nitride semiconductor layer and a gate structure. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The barrier layer is disposed on the second nitride semiconductor layer and has a bandgap greater than that of the second nitride semiconductor layer. The third nitride semiconductor layer is doped with impurity and disposed on the barrier layer. The gate structure is disposed on the third nitride semiconductor layer.

A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer containing aluminum located on the first nitride semiconductor layer, a third nitride semiconductor layer with an aluminum concentration higher than that of the second nitride semiconductor layer located on the second nitride semiconductor layer, a drain electrode and a source electrode provided on one of the second nitride semiconductor layer and on the third nitride semiconductor layer, and a gate electrode located between the drain electrode and the source electrode.

A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.

A nitride semiconductor device 1 includes a first nitride semiconductor layer that constitutes an electron transit layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, a gate portion that is formed on the second nitride semiconductor layer, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are opposingly disposed across the gate portion. The gate portion includes a third nitride semiconductor layer of a ridge shape that is formed on the second nitride semiconductor layer and contains an acceptor type impurity and a gate electrode that is formed on the third nitride semiconductor layer. A film thickness of the third nitride semiconductor layer is greater than 100 nm.

In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d.sub.1, a lower p-doped Group III nitride layer having a thickness d.sub.2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped Al.sub.xGa.sub.1-xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness d.sub.2 of the lower p-doped Group III nitride layer is larger than the thickness d.sub.1 of the upper p-doped GaN layer.

The present invention relates to a heterojunction field effect transistor, and the heterojunction field effect transistor includes a barrier layer provided in an upper layer portion of a channel layer of a first nitride semiconductor, being formed of a second nitride semiconductor hetero-joined to the first nitride semiconductor, first and second impurity regions provided, being spaced each other with the barrier layer interposed therebetween, a source electrode and a drain electrode which are provided on the first and second impurity regions, respectively, an insulating film which is so provided as to come into contact with at least a region of the barrier layer excluding an edge portion thereof on the side of the source electrode, a gate insulating film which is in contact with the edge portion of the barrier layer and covers the insulating film, and a gate electrode which is so provided on the gate insulating film.

A semiconductor device including a substrate, a seed layer, a buffer layer, a channel layer, a barrier layer, a gate structure, a first source/drain structure, a second source/drain structure, and a contact is provided. The seed layer is disposed on the substrate. The buffer layer is disposed on the seed layer. The channel layer is disposed on the buffer layer. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The first and second source/drain structures are disposed on opposite sides of the gate structure. The contact contacts the first source/drain structure. The distance between the gate structure and the contact is between 0.5 micrometers and 30 micrometers.

A semiconductor device having a substrate, a pair of Group III-Nitride layers on the substrate forming: a heterojunction with a 2 Dimensional Electron Gas (2DEG) channel in a lower one of the pair of Group III-Nitride layers, a cap beryllium doped Group III-Nitride layer on the upper one of the pair of Group III-Nitride layers; and an electrical contact in Schottky contact with a portion of the cap beryllium doped, Group III-Nitride layer.

In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.

A nitride semiconductor device includes an electron transfer layer formed from a nitride semiconductor, an electron supplying layer formed from a nitride semiconductor having a larger band gap than the electron transfer layer on the electron transfer layer, a first step layer formed from a nitride semiconductor having a smaller band gap than the electron supplying layer on part of the electron supplying layer, a second step layer formed from a nitride semiconductor having a larger band gap than the first step layer on the first step layer, a gate layer including an acceptor impurity and formed from a nitride semiconductor having a smaller band gap than the second step layer on the second step layer, a gate electrode formed on the gate layer, and a source electrode and a drain electrode. The first step layer includes a first extension extending outward from the gate layer in plan view.