A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1):

[00001]$\begin{array}{cc}{d}_g\sqrt{\frac{2E_{F}q\left(N_{\mathrm{DA}}+N_A-N_{\mathrm{DD}}-N_D\right)}{{\mathrm{.Math.}}_0{\mathrm{.Math.}}_C}}+{\Phi }_B-\frac{d_{B}P}{{\mathrm{.Math.}}_0{\mathrm{.Math.}}_C}>0& \left(1\right)\end{array}$

A transistor device including a layer of AlGaN extending between a source and drain of the device; a GaN channel layer extending under the AlGaN layer; a gate stack including a layer of p-doped gallium nitride; and a layer of p-doped InGaN of at least 5 nm in thickness positioned between the AlGaN layer and the p-doped gallium nitride layer, the InGaN layer having a length greater than a length of the gate stack.

A high electron mobility transistor (HEMT) device including a substrate, a first channel layer, a second channel layer, a cap layer, a first metal nitride layer, a gate, a source, and a drain is provided. The first channel layer is disposed on the substrate. The second channel layer is disposed on the first channel layer. The cap layer is disposed on the second channel layer and exposes a portion of the second channel layer. The first metal nitride layer is disposed on the cap layer. The gate is disposed on the first metal nitride layer. The width of the first metal nitride layer is greater than or equal to the width of the gate. The source and the drain are disposed on the second channel layer at two sides of the gate.

Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

A semiconductor structure includes a substrate, a channel layer, a barrier layer, a source structure, a drain structure, a doped compound semiconductor layer, a dielectric layer, and a gate structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source structure and the drain structure are disposed on opposite sides of the barrier layer. The doped compound semiconductor layer is disposed on the barrier layer. The doped compound semiconductor layer has a first side adjacent to the source structure and a second side adjacent to the drain structure. The doped compound semiconductor layer has at least one opening exposing at least a portion of the barrier layer. The dielectric layer is disposed on the doped compound semiconductor layer and the barrier layer. The gate structure is disposed on the doped compound semiconductor layer.

A nitride semiconductor device includes an electron transit layer formed from a nitride semiconductor, an electron supply layer formed on the electron transit layer from a nitride semiconductor having a larger band gap than the electron transit layer, a gate layer formed on the electron supply layer from a nitride semiconductor including an acceptor impurity, a gate electrode formed on the gate layer, and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode and including first and second openings separated in a first direction, the gate layer being disposed therebetween, a source electrode contacting the electron supply layer through the first opening, a drain electrode contacting the electron supply layer through the second opening, and an auxiliary electrode formed above the electron supply layer, directly covered by the passivation layer, and disposed between the gate electrode and the drain electrode in plan view.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, and an insulating member. The third electrode in a first direction is between the first and second electrodes in the first direction. The first direction is from the first toward second electrode. The first semiconductor layer includes Al.sub.x1Ga.sub.1-x1N (0≤x1<1), and first to sixth partial regions. A second direction from the first partial region toward the first electrode crosses the first direction. The second semiconductor layer includes Al.sub.x2Ga.sub.1-x2N (0<x2<1 and x1<x2), and first and second semiconductor regions. A direction from the fourth partial region toward the first semiconductor region is along the second direction. A direction toward the second semiconductor region from the fifth and sixth partial regions is along the second direction. The insulating member includes first to third insulating regions.

A semiconductor device is provided, including a substrate, a gate electrode, a first dielectric layer, a source field plate, a second dielectric layer, a source electrode and a drain electrode. The gate electrode is disposed on the substrate. The first dielectric layer is disposed on the gate electrode and has a first recess and a second recess. The source field plate is disposed on the first dielectric layer and extends into the first recess and the second recess. The second dielectric layer is disposed on the source field plate. The source electrode is disposed on the second dielectric layer and electrically connected to the source field plate. The drain electrode is disposed on the second dielectric layer. The first recess and the second recess are located between the gate electrode and the drain electrode.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.