According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions. The semi-insulating layer contacts the second electrode, the first conductive layer, and the third electrode.

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions. The semi-insulating layer contacts the second electrode, the first conductive layer, and the third electrode.

A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

In an edge termination region, a second gate runner for a current sensor is formed between a first gate runner for a main semiconductor device and an active region. The second gate runner surrounds the periphery of the active region in a substantially rectangular shape having an opening. One end of the second gate runner is connected to all of the gate electrodes of the current sensor, and the other end is connected to the first gate runner at between a gate pad and an OC pad. This makes it possible to increase the gate capacitance of the current sensor as the current sensor switches ON and OFF when a pulse-shaped gate voltage is applied to the gate pad by an amount proportional to the surface area of the second gate runner.

A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.