Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

The various embodiments described herein include methods, devices, and systems for fabricating and operating transistors. In one aspect, a transistor includes: (1) a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and (2) a superconducting component configured to operate in a superconducting state while: (a) a temperature of the superconducting component is below a superconducting threshold temperature; and (b) a first current supplied to the superconducting component is below a current threshold; where: (i) the semiconducting component is located adjacent to the superconducting component; and (ii) in response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state.

The various implementations described herein include methods, devices, and systems for detecting light. In one aspect, a photodetector device includes: a superconducting wire, and a transistor that includes a semiconducting component and a superconducting component. The superconducting wire is electrically coupled to the superconducting component. The semiconducting component is located adjacent to the superconducting component. The superconducting component is configured to, in response to receiving an input current exceeding a current threshold, transition from a superconducting state to a non-superconducting state and generate heat sufficient to increase a temperature of the semiconducting component from a temperature below a semiconducting threshold temperature to a temperature above the semiconducting threshold temperature.

Provided is a BOA liquid crystal panel based on an IGZO-TFT and a method for manufacturing the same. The method includes steps of: (1) forming a black matrix; (2) forming a gate; (3) forming a gate insulator; (4) forming a source and a drain; (5) forming IGZO; (6) forming a passivation; (7) forming R/G/B color resist; (8) forming ITO. Copper oxide is used as a coplanar structure of the black matrix of an IGZO-TFT based BOA component, which can effectively prevent the risk of etching IGZO.

The present disclosure relates to semiconductor based Josephson junctions and their applications within the field of quantum computing, in particular a tuneable Josephson junction device has been used to construct a gateable transmon qubit. One embodiment relates to a Josephson junction comprising an elongated hybrid nanostructure comprising superconductor and semiconductor materials and a weak link, wherein the weak link is formed by a semiconductor segment of the elongated hybrid nanostructure wherein the superconductor material has been removed to provide a semiconductor weak link.

The various embodiments described herein include methods, devices, and systems for fabricating and operating transistors. In one aspect, a transistor includes: (1) a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and (2) a superconducting component configured to operate in a superconducting state while: (a) a temperature of the superconducting component is below a superconducting threshold temperature; and (b) a first current supplied to the superconducting component is below a current threshold; where: (i) the semiconducting component is located adjacent to the superconducting component; and (ii) in response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state.

Provided is a BOA liquid crystal panel based on an IGZO-TFT and a method for manufacturing the same. The method includes steps of: (1) forming a black matrix; (2) forming a gate; (3) forming a gate insulator; (4) forming a source and a drain; (5) forming IGZO; (6) forming a passivation; (7) forming R/G/B color resist; (8) forming ITO. Copper oxide is used as a coplanar structure of the black matrix of an IGZO-TFT based BOA component, which can effectively prevent the risk of etching IGZO.

A semiconductor device includes a substrate. A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially disposed on the substrate. A source structure is formed in the first dielectric layer. A drain structure is formed in the third dielectric layer. A channel structure extends through the second dielectric layer and directly contacts the source structure and the drain structure. A gate structure is disposed at two sides of the channel structure. The gate structure includes a conductive layer and a gate dielectric layer. The gate dielectric layer is along sidewalls and a bottom surface of the conductive layer, and is interposed between the conductive layer and the channel structure and the second dielectric layer.