Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

Methods and systems disclosed herein can measure thin film stacks, such as film on grating and bandgap on grating in semiconductors. For example, the thin film stack may be a 1D film stack, a 2D film on grating, or a 3D film on grating. One or more effective medium dispersion models are created for the film stack. Each effective medium dispersion model can substitute for one or more layers. A thickness of one or more layers can be determined using the effective medium dispersion based scatterometry model. In an instance, three effective medium dispersion based scatterometry models are developed and used to determine thickness of three layers in a film stack.

A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method includes providing a substrate, where the substrate includes a device region and a peripheral region; and forming a bit line structure in the device region, and forming a transistor structure in the peripheral region, where the transistor structure includes a gate structure, and the bit line structure includes a bit line conductive layer and a bit line protective layer; the gate structure includes a gate oxide layer, a high-k dielectric layer, a gate conductive layer and a gate protective layer; the gate conductive layer and the bit line conductive layer are obtained by patterning a same conductive material layer, and the bit line protective layer and the gate protective layer are obtained by patterning a same protective material layer.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method includes providing a substrate, where the substrate includes a device region and a peripheral region; and forming a bit line structure in the device region, and forming a transistor structure in the peripheral region, where the transistor structure includes a gate structure, and the bit line structure includes a bit line conductive layer and a bit line protective layer; the gate structure includes a gate oxide layer, a high-k dielectric layer, a gate conductive layer and a gate protective layer; the gate conductive layer and the bit line conductive layer are obtained by patterning a same conductive material layer, and the bit line protective layer and the gate protective layer are obtained by patterning a same protective material layer.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is inhibited and reliability is improved. The transistor includes a first gate electrode; a first insulating film over the first gate electrode; an oxide semiconductor film over the first insulating film; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; and a second gate electrode over the second insulating film. The second insulating film includes oxygen. The second gate electrode includes the same metal element as at least one of metal elements of the oxide semiconductor film and has a region thinner than the oxide semiconductor film.

A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.