A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.

A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).

The present invention relates to a voltage-controllable capacitor comprising a first electrode layer (4) composed of a non-ferroelectric material, said first electrode layer being applied on a substrate (6), a ferroelectric interlayer (3) having a thickness that is less than the thickness of the first electrode layer (4), and a second electrode layer (2) composed of a non-ferroelectric material. The ferroelectric interlayer (3) is arranged between the first electrode layer (4) and the second electrode layer (2).

An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls. The pair of walls individually have a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions. Other embodiments, including methods, are disclosed.

NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

A method in a memory circuit for rapidly determining the location of a file includes (a) associating the file with a timestamp and a unique identifier index number when the file is stored or updated in the memory circuit, and storing in a look-up table in the memory circuit the associated timestamp and an address associated with where the file is stored; (b) receiving a search request that specifies a unique identifier index number of a file to be located; and (c) using exclusive-or (XOR) circuits or content addressable memory (CAM) circuits to compare the unique identifier index number in the search request with the unique identifier index number stored in the look-up table, and reporting, when a match is found between the unique identifier index number in the search request and the unique identifier index number stored in the look-up table, the timestamp and address associated with the match.

A method in a memory circuit for rapidly determining the location of a file includes (a) associating the file with a timestamp and a unique identifier index number when the file is stored or updated in the memory circuit, and storing in a look-up table in the memory circuit the associated timestamp and an address associated with where the file is stored; (b) receiving a search request that specifies a unique identifier index number of a file to be located; and (c) using exclusive-or (XOR) circuits or content addressable memory (CAM) circuits to compare the unique identifier index number in the search request with the unique identifier index number stored in the look-up table, and reporting, when a match is found between the unique identifier index number in the search request and the unique identifier index number stored in the look-up table, the timestamp and address associated with the match.