The present application provides a chip package structure and an electronic device, which could reduce a chip package thickness and implement ultra-thinning of chip package. The chip package structure includes a chip, a substrate, a lead and a lead protection adhesive; the lead is configured to electrically connect the chip and the substrate; the lead protection adhesive is configured to support the lead, where a highest point of the lead protection adhesive is not higher than a highest point of an upper edge of the lead.

A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

A charged particle beam system may include a detector. A package for a detector may have a package body that includes two sets of pins, each of the sets of pins including two pins. Each pin of the sets of pins may be configured to be connected to one of two terminals of a sensing element. Pins of different sets may be configured to be connected to a different one of the two terminals of the diode. The sets of pins may be arranged with a symmetry such that magnetic fields generated when current passes through the sets of pins is reduced due to the symmetry.

A sensor device according to the present disclosure includes a Peltier element, a sensor element thermally connected to a cooling surface of the Peltier element, and a window member that faces a light receiving surface of the sensor element and is made of borosilicate glass.

A light sensor includes a photodiode, interlayer dielectric layer and plurality of metal layers. A polarizer is disposed in the plurality of metal layers. The photodiode is coupled to generate charge in response to incident light directed through a first side of the semiconductor layer. The polarizer includes a first metal grid formed with a first metal layer and a second metal grid formed with a third metal layer. The second metal grid is stacked with the first metal grid such that the first and second metal grids are disposed above and aligned with the photodiode. The photodiode is optically coupled to receive incident light through the first and second metal grids of the polarizer and through the first side of the semiconductor layer.

A semiconductor package structure includes a carrier, an electronic device, a spacer, a transparent panel, and a conductive wire. The electronic device has a first surface and an optical structure on the first surface. The spacer is disposed on the first surface to enclose the optical structure of the electronic device. The transparent panel is disposed on the spacer. The conductive wire electrically connects the electronic device to the carrier and is exposed to air.

This invention provides a light-concentrating structure with photosensitivity enhancing effect, including the substrate, buried layer, first electrode layer, second electrode layer, dielectric layer and interconnection structure. The substrate is equipped with a housing space; the buried layer is arranged above the substrate with the housing space; the first electrode layer is arranged above the buried layer; the second electrode layer is arranged in the middle of the first electrode layer; the dielectric layer is arranged above the second electrode layer; the interconnection structure is arranged above the substrate and the first electrode layer surrounding the dielectric layer, which forms an opening and a light-concentrating recess groove.

The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

An optoelectronic component includes a radiation side, a contact side opposite the radiation side having at least two electrically conductive contact elements, and a semiconductor layer sequence having an active layer that emits or absorbs the electromagnetic radiation, wherein the at least two electrically conductive contact elements have different polarities, are spaced apart from each other and are completely or partially exposed at the contact side in an unmounted state of the optoelectronic component, a region of the contact side is partially or completely covered with an electrically insulating, contiguously formed cooling element, the cooling element is in direct contact with the contact side and has a thermal conductivity of at least 30 W/(m.Math.K), and in a plan view of the contact side, the cooling element partially covers one or both of the at least two electrically conductive contact elements.