A photovoltaic device includes: a p- or n-type semiconductor substrate; a p-type amorphous semiconductor film and an n-type amorphous semiconductor film on a first-face side; p-electrodes on the p-type amorphous semiconductor film; and n-electrodes on the n-type amorphous semiconductor film, wherein: the p-electrodes and the n-electrodes are arranged at intervals; the p-type amorphous semiconductor film surrounds the n-type amorphous semiconductor film in an in-plane direction of the semiconductor substrate; the n-type amorphous semiconductor film has an edge portion providing an overlapping region where the n-type amorphous semiconductor film overlaps the p-type amorphous semiconductor film; and the n-electrodes are disposed in areas of the n-type amorphous semiconductor film that are surrounded by the overlapping region.

The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

A semiconductor device includes a photosensitive element, an insulating region, and a quench element. The photosensitive element includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type on the first semiconductor region, a third semiconductor region of a second conductivity type on the second semiconductor region, and a fourth semiconductor region of the second conductivity type around the second and third semiconductor regions. An impurity concentration of the first conductivity type in the second semiconductor region is higher than that in the first semiconductor region. An impurity concentration of the second conductivity type in the fourth semiconductor region is lower than that of the third semiconductor region. The insulating region is around the first and fourth semiconductor regions. The quench element is electrically connected to the third semiconductor region.

The embodiments of the present disclosure provide a photoelectric sensor and a method of manufacturing the same, and a display panel. The photoelectric sensor includes a transparent substrate, a hole transport layer, a light absorption layer, and an electron transport layer. Disposing the hole transport layer on one side close to the transparent substrate and shielding the hole transport layer by use of the light absorption layer and the electron transport layer avoid the dissolution of molybdenum oxide in the hole transport layer during a cleaning process and reduce the difficulty in manufacturing process of the photoelectric sensor.

A solar cell has a P-type silicon substrate in which one main surface is a light-receiving surface and another main surface is a backside, a dielectric film on the backside, and an N-conductivity type layer in at least a part of the light-receiving surface of the P-type silicon substrate, wherein the P-type silicon substrate is a silicon substrate doped with gallium, and the backside of the P-type silicon substrate contains a diffused group III element. This provides a solar cell with excellent conversion efficiency provided with a gallium-doped substrate, and a method for manufacturing the same.

Example embodiments relate to controlling detection time in photodetectors. An example embodiment includes a device. The device includes a substrate. The device also includes a photodetector coupled to the substrate. The photodetector is arranged to detect light emitted from a light source that irradiates a top surface of the device. A depth of the substrate is at most 100 times a diffusion length of a minority carrier within the substrate so as to mitigate dark current arising from minority carriers photoexcited in the substrate based on the light emitted from the light source.

An optoelectronic semiconductor structure is revealed. The optoelectronic semiconductor structure includes a substrate, a first electrode, an electrode contact, a semiconductor layer, and a second electrode. After a photoactive layer of the semiconductor structure absorbs energy from a light source to generate an exciton, the exciton dissociates into a first carrier and a second carrier. The first carrier is transferred to the first electrode through the first interface layer while the second carrier is transferred from the second electrode to the electrode contact directly by a tunneling effect.

A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.

A semiconductor layer sequence includes a first nitridic compound semiconductor layer, a second nitridic compound semiconductor layer, and an intermediate layer arranged between the first and second nitridic compound semiconductor layers. Beginning with the first nitridic compound semiconductor layer, the intermediate layer and the second nitridic compound semiconductor layer are arranged one after the other in a direction of growth of the semiconductor layer sequence and are adjacent to each other in direct succession. The intermediate layer has a lattice constant different from the lattice constant of the first nitridic compound semiconductor layer at least at some points. The second nitridic compound semiconductor layer is lattice-adapted to the intermediate layer at least at some points.

The present disclosure provides a semiconductor device and a semiconductor component. The semiconductor device includes an active structure, a ring-shaped semiconductor contact layer, a first electrode, and an insulating layer. The active structure has a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer located between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. The ring-shaped semiconductor contact layer is located on the second-conductivity-type semiconductor layer and having a first inner sidewall and a first outer sidewall. The first electrode has an upper surface and covers the ring-shaped semiconductor contact layer. The insulating layer covers the first electrode and the active structure and has a second inner sidewall and a second outer sidewall. The first inner sidewall is not flush with the second inner sidewall in a vertical direction.