Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having at least one diode region; forming at least one first fin on the semiconductor substrate in the diode region; forming a first doped layer containing a first type of doping ions having a first conductivity in the first fin; and forming a second doped layer doped containing a second type of doping ions having a second conductivity opposite to the first conductivity on the first doped layer. A size of an interface between the first doped layer and the second doped layer along a width direction of the first fin is greater than a width of the first fin.

A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.

A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.

To prevent a leakage current in a semiconductor integrated circuit in which a plurality of semiconductor substrates is laminated with a through-silicon via. Into a silicon substrate, one of P-type impurities and N-type impurities is implanted at a predetermined concentration. Into a plurality of channels, the other of the P-type impurities and the N-type impurities is implanted at a higher concentration than the predetermined concentration on one surface of the silicon substrate. An electrode is formed in each of the plurality of channels. Into a well layer, the same impurities as in the silicon substrate are implanted at a higher concentration than the predetermined concentration between the other surface of the silicon substrate and the plurality of channels.

A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant can not enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.

A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

An image sensing device includes an image sensor including a first sub-pixel array and a second sub-pixel array. The first sub-pixel array includes a plurality of first pixels having a first color filter, and the second sub-pixel array includes a plurality of second pixels having a second color filter and a plurality of third pixels for phase detection. The image sensor may generate first pixel values from the first pixels, second pixel values from the second pixels and third pixel values from the third pixels. The image sensing device also includes an image processor suitable for generating a first image value corresponding to the first sub-pixel array based on the first pixel values and generating a second image value corresponding to the second sub-pixel array based on the first to third pixel values.

The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.