H01L31/062

Image sensor

An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Stacked semiconductor dies with a conductive feature passing through a passivation layer

A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

Concave reflector for complementary metal oxide semiconductor image sensor (CIS)

In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

CMOS image sensor with shallow trench edge doping

In some embodiments, the present disclosure relates to an integrated chip having a photodetector arranged within a semiconductor substrate having a first doping type. One or more dielectric materials are disposed within a trench defined by interior surfaces of the semiconductor substrate. A doped epitaxial material arranged within the trench at a location laterally between the one or more dielectric materials and the photodetector. The doped epitaxial material has a second doping type that is different than the first doping type.

3D semiconductor device with isolation layers

A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.

Solid state imaging device and imaging apparatus with pixel column having multiple output lines
10658404 · 2020-05-19 · ·

The present technology relates to a solid state imaging device capable of providing a solid state imaging device that does not cause deterioration of image quality due to an increase in reading speed of a pixel signal, and an imaging apparatus. In a pixel array block in which a plurality of pixels are two-dimensionally arrayed, each of the pixels including: a photoelectric conversion device; a plurality of transistors to be used for reading a signal from the photoelectric conversion device; and wiring for driving the transistors, a plurality of pixel output lines are provided for each one column of the plurality of pixels two-dimensionally arrayed, and the plurality of pixel output lines from the pixels are arranged separately in a plurality of wiring layers. The present technology can be applied to, for example, a CMOS image sensor.

Image sensor

An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Image sensor

An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Wafer-level optical structure

A wafer-level optical structure includes at least two optical lens sets disposed on an optically transparent wafer, at least one trench disposed between two adjacent optical lens sets to divide the two adjacent optical lens sets, at least one spacer disposed between two adjacent optical lens sets to be correspondingly and partially disposed in the trench, and an adhesive disposed inside the trench.

Method of fabricating an emitter region of a solar cell

Methods of fabricating emitter regions of solar cells are described. Methods of forming layers on substrates of solar cells, and the resulting solar cells, are also described.