A semiconductor device in a first area includes first non-planar semiconductor structures separated with a first distance, and a first isolation region including a first layer and a second layer that collectively embed a lower portion of each of the first non-planar semiconductor structures. At least one of the first layer or second layer of the first isolation region is in a cured state. The semiconductor device in a second area includes second non-planar semiconductor structures separated with a second distance, and a second isolation region including a first layer and a second layer that collectively embed a lower portion of each of the second non-planar semiconductor structures. At least one of the first or second layer of the second isolation region is in a cured state.

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Methods of the disclosure include a BN ALD process at low temperatures using a reactive nitrogen precursor, such as thermal N.sub.2H.sub.4, and a boron containing precursor, which allows for the deposition of ultra thin (less than 5 nm) films with precise thickness and composition control. Methods are self-limiting and provide saturating atomic layer deposition (ALD) of a boron nitride (BN) layer on various semiconductors and metallic substrates.

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.

The image sensing device includes a pixel region in a pixel array area and a dummy pixel region in a periphery area. The pixel region includes a radiation region, a floating diffusion region, a transfer transistor, a source-follower transistor, a reset transistor and a select transistor. The dummy pixel region includes a radiation region and a floating diffusion region. A gate of one of the transfer transistor, the reset transistor and the select transistor in the pixel region is electrically connected to the radiation region or the floating diffusion region in the dummy pixel region.

Image sensors may include hybrid three-dimensional imaging pixel groups. The pixel groups may be capable of obtaining both phase detection information and time-of-flight information. A pixel group may have first and second photodiodes covered by a single microlens that are used to obtain phase detection information. The microlens may also cover a third photodiode that obtains time-of-flight information. The first and second photodiodes may be formed in a first substrate whereas the third photodiode may be formed in a second substrate. The first and second substrates may be connected by a metal interconnect layer.

The present technology relates to a solid-state imaging element, an imaging device, and an electronic apparatus which enable enhancement of focusing accuracy and sensitivity and suppression of color mixing, in a high image height portion. Incident light is condensed by a main lens, and the condensed light is condensed by a plurality of on-chip lenses. The on-chip lenses are each shared by a plurality of photodiodes that receive the light condensed by the on-chip lens and that generate and accumulate electric charges corresponding to the amounts of light. The plurality of photodiodes sharing the on-chip lens are shaped, in accordance with the image height of the on-chip lens, in such a manner as to have substantially uniform light reception characteristics. The present technology is applicable to a CMOS image sensor.

A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.