A four junction solar cell and its method of manufacture including an upper first solar subcell composed of a semiconductor material having a first band gap; a second solar subcell adjacent to said first solar subcell and composed of a semiconductor material having a second band gap smaller than the first band gap and being lattice matched with the upper first solar subcell; a third solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a third band gap smaller than the second band gap and being lattice matched with the second solar subcell; a graded interlayer adjacent to the third solar subcell and having a fourth band gap greater than the third band gap; and a bottom solar subcell adjacent to the graded interlayer and being lattice mismatched from the third solar subcell and having a fifth band gap smaller than the fifth band gap, wherein the selection of composition of the subcells and their band gaps maximizes the efficiency of the solar cell at a predetermined temperature value (between 28 and 70 degrees Centigrade) at a predetermined time after the initial deployment in space, (the time of the initial deployment being referred to as “beginning-of-life (BOL)”), such predetermined time being referred to as the “end-of-life (EOL)” time, and such time being at least one year.

A p+ or n+ type doping process for semiconductors, allows to implement a semiconductor with a highly doped surface layer, and it comprises the steps of: providing a substrate made of semiconductor material; depositing on a surface of 5 the substrate made of semiconductor material a thin source layer made of dopant material acting as dopant source; depositing on said source layer an additional protective surface layer made of semiconductor material; inducing liquefaction of the surface layer at least until the source layer; and cooling down the substrate surface so as to obtain the diffusion of the dopant material.

A superconductor tape and method for fabricating same are disclosed. Embodiments are directed to a superconductor tape including a substrate and a buffer stack. In one embodiment, the buffer stack includes: an Ion Beam-Assisted Deposition (IBAD) template layer above the substrate; a homo-epitaxial film of MgO or TiN above the IBAD template layer; an epitaxial film of silver above the homo-epitaxial film; and a homo-epitaxial film of LaMnO3 (LMO) above the silver epitaxial film. The superconductor tape also includes a superconductor film above the buffer stack. These and other embodiments achieve a LMO film with substantially improved texture, resulting in a superconductor structure having high critical current and significantly reduced power consumption and cost.

An avalanche photodiode (APD) device, in particular, a lateral separate absorption charge multiplication (SACM) APD device, and a method for its fabrication is provided. The APD device comprises a first contact region and a second contact region formed in a semiconductor layer. Further, the APD device comprises an absorption region formed on the semiconductor layer, wherein the absorption region is at least partly formed on a first region of the semiconductor layer, wherein the first region is arranged between the first contact region and the second contact region. The APD device further includes a charge region formed in the semiconductor layer between the first region and the second contact region, and an amplification region formed in the semiconductor layer between the charge region and the second contact region. At least the absorption region is curved on the semiconductor layer.

A photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, wherein the N-doped waveguide structure comprises a plurality of first fins. Each adjacent pair of the plurality of first fins is separated by a trench formed in the semiconductor material. The photodetector also includes a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. The detector structure comprises a single crystal semiconductor material. The photodetector also includes a first diffusion region that extends from the bottom surface of the trench into the semiconductor material, wherein the first diffusion region comprises atoms of the single crystal semiconductor material of the detector structure.

A photodetector includes a photodetecting region in a semiconductor substrate, and a reflector extending at least partially along a sidewall of the photodetecting region in the semiconductor substrate. The reflector includes an air gap defined in the semiconductor substrate. The reflector allows use of thinner germanium for the photodetecting region. The air gap may have a variety of internal features to direct electromagnetic radiation towards the photodetecting region.

Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.

A single photon avalanche (SPAD) device configured to detect visible to infrared light includes a substrate and a trench coupled to the substrate. The trench has a lattice mismatch with the substrate and has a height equal to or greater than its width. The device further includes a substantially defect-free semiconductor region that includes photosensitive material. The semiconductor region includes a well coupled to the trench and doped a first type. The well is configured to detect a photon and generate a current. The semiconductor region also includes a region formed in the well and doped a second type opposite to the first type. The well is configured to cause an avalanche multiplication of the current. The trench and the well form a first electrode and the region forms a second electrode.

Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.

The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.