A doped photovoltaic device is presented. The photovoltaic device includes a semiconductor absorber layer or stack disposed between a front contact and a back contact. The absorber layer comprises cadmium, selenium, and tellurium doped with Ag, and optionally with Cu. The Ag dopant may be added to the absorber in amounts ranging from 5×10.sup.15/cm.sup.3 to 2.5×10.sup.17/cm.sup.3 via any of several methods of application before, during, or after deposition of the absorber layer. The photovoltaic device has improved Fill Factor and P.sub.MAX at higher P.sub.r(=I.sub.sc*V.sub.oc product) values, e.g. about 160 W, which results in improved conversion efficiency compared to a device not doped with Ag. Improved PT may result from increased I.sub.sc, increased V.sub.oc, or both.

Photo-detector comprising: photo absorbing layer exhibiting a valence band energy level; a barrier layer, first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers between the photo absorbing layer and contact area, and block the flow of thermalized majority carriers between the photo absorbing layer and contact area. The photoabsorber layer extends past the one or more individual sections of the contact layer in the direction across the photodetector, and is monolithically provided for each of the individuals detector elements.

Disclosed herein is an apparatus and a method of making the apparatus. The method comprises obtaining a plurality of semiconductor single crystal chunks. Each of the plurality of semiconductor single crystal chunks may have a first surface and a second surface. The second surface may be opposite to the first surface. The method may further comprise bonding the plurality of semiconductor single crystal chunks by respective first surfaces to a first semiconductor wafer. The plurality of semiconductor single crystal chunks forming a radiation absorption layer. The method may further comprise forming a plurality of electrodes on respective second surfaces of each of the plurality of semiconductor single crystal chunks, depositing pillars on each of the plurality of semiconductor single crystal chunks and bonding the plurality of semiconductor single crystal chunks to a second semiconductor wafer by the pillars.

The present invention proposes a method to form a double-graded CdSeTe thin film. The method comprises providing a base substrate, forming a first CdSe.sub.wTe.sub.1-w layer having a first amount w1 of selenium in it, forming a second CdSe.sub.wTe.sub.1-w layer having a second amount w2 of selenium in it and forming a third CdSe.sub.wTe.sub.1-w layer having a third amount w3 of selenium in it. The second amount w2 lies in the range between 0.25 and 0.4, whereas each of the amounts w1 and w3 lies in the range extending from 0 to 1. According to the present invention, the energy gap in the first and the third CdSe.sub.wTe.sub.1-w layers is equal to or higher than 1.45 eV and the energy gap in the second CdSe.sub.wTe.sub.1-w layer lies in the range between 1.38 eV and 1.45 eV and is smaller than the energy gap in the first and the third CdSe.sub.wTe.sub.1-w layers.

An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

A photodetector comprising a photoabsorber, comprising a doped semiconductor, a contact layer comprising a doped semiconductor and a barrier layer comprising a charge carrier compensated semiconductor, the barrier layer compensated by doping impurities such that it exhibits a valence band energy level substantially equal to the valence band energy level of the photo absorbing layer and a conduction band energy level exhibiting a significant band gap in relation to the conduction band of the photo absorbing layer, the barrier layer disposed between the photoabsorber and contact layers. The relationship between the photo absorbing layer and contact layer valence and conduction band energies and the barrier layer conduction and valance band energies is selected to facilitate minority carrier current flow while inhibiting majority carrier current flow between the contact and photo absorbing layers.

Photo-detection device (100) including a semiconductor substrate (110) made of Cd.sub.xHg.sub.1-xTe, with an N-doped region (120), a P-doped region (130), and a concentrated casing (150) only located in the P-doped region and having an average cadmium concentration greater than the average cadmium concentration in the N-doped region.

According to the invention, the concentrated casing (150) has a cadmium concentration gradient, defining therein at least one intermediate gap zone (151) and at least one high gap zone (152), and the intermediate gap zone (151) is in direct physical contact with an electrical contact block (170).

A significant reduction in the dark current and an optimal charge carrier collection are thus combined.

An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. The configuration of the dielectric structures and the photosensitive material promote total internal reflection of light within a passivation layer.