Patent classifications
H01L31/1852
Multijunction metamorphic solar cell
A four junction solar cell and its method of manufacture including an upper first solar subcell composed of a semiconductor material having a first band gap; a second solar subcell adjacent to said first solar subcell and composed of a semiconductor material having a second band gap smaller than the first band gap and being lattice matched with the upper first solar subcell; a third solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a third band gap smaller than the second band gap and being lattice matched with the second solar subcell; a graded interlayer adjacent to the third solar subcell and having a fourth band gap greater than the third band gap; and a bottom solar subcell adjacent to the graded interlayer and being lattice mismatched from the third solar subcell and having a fifth band gap smaller than the fifth band gap, wherein the selection of composition of the subcells and their band gaps maximizes the efficiency of the solar cell at a predetermined temperature value (between 28 and 70 degrees Centigrade) at a predetermined time after the initial deployment in space, (the time of the initial deployment being referred to as “beginning-of-life (BOL)”), such predetermined time being referred to as the “end-of-life (EOL)” time, and such time being at least one year.
Multijunction solar cell assembly
A multijunction solar cell assembly and its method of manufacture including interconnected first and second discreate semiconductor body subassemblies disposed adjacent and parallel to each other, in the sense of the incoming illumination, each semiconductor body subassembly including first top subcell, and possibly third middle subcells and a bottom solar subcell; wherein the interconnected subassemblies form at least a Three junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor body with its at least least two junctions and the bottom solar subcell in the second semiconductor body representing the additional junction.
Avalanche Photodiode and Method for Manufacturing Same
A substrate, a first n-type contact layer, a buffer layer, a multiplication layer, an electric field control layer, an absorption layer, and a p-type contact layer are provided. An electrically conductive layer is formed in a central portion of the buffer layer. The substrate is made of a semiconductor having thermal conductivity higher than that of InP, such as SiC, and the first n-type contact layer is made of the same semiconductor as that of the substrate but having n-type conductivity. An n electrode is formed over the first n-type contact layer via a second n-type contact layer.
COMPOSITE SUBSTRATE FOR FABRICATING III-V PHOTODETECTOR ARRAYS
A method for forming a composite substrate containing layers of dissimilar materials is provided. The method includes a step of disposing a release layer over a base substrate where the base substrate is composed of a first material. A template layer is attached to the release layer. Characteristically, the template layer is composed of a second material and adapted to form a compound semiconductor device thereon.
Multijunction solar cell
A multijunction solar cell including a substrate and a top (or light-facing) solar subcell having an emitter layer, a base layer, and a window layer adjacent to the emitter layer, the window layer composed of a material that is optically transparent, has a band gap of greater than 2.6 eV, and includes an appropriately arranged multilayer antireflection coating on the top surface thereof.
METHOD OF MANUFACTURING III-V GROUP NANOROD SOLAR CELL SO THAT SUBSTRATE CAN BE REUSED
Disclosed is a method of manufacturing a III-V group nanorod solar cell so that a substrate can be reused. The method may includes a first growth process of forming an etch stop layer on a substrate, a second growth process of growing a sacrificial layer on the etch stop layer, a third growth process of forming, on the sacrificial layer, a pattern layer including an opening at each location at which each nanorod solar cell is able to be grown, a fourth growth process of growing the nanorod solar cells on the sacrificial layer through the openings within the pattern layer, a forming process of forming a solar cell protection layer on outsides of the nanorod solar cells, a first etching process of etching the sacrificial layer and the pattern layer, and a second etching process of etching the etch stop layer.
Water soluble oxide liftoff layers for GaAs photovoltaics
Disclosed herein are compositions, methods and devices that allow for water-soluble epitaxial lift-off of III-V. Epitaxial growth of STO/SAO templates on STO (001) and Ge (001) substrates were demonstrated. Partially epitaxial GaAs growth was achieved on STO/SAO/STO substrate templates.
Light source assembly, optical sensor assembly, and method of manufacturing a cell of the same
A light source assembly includes a plurality of cells and a driving circuit. Each of the cells includes a transistor and a light source. The transistor includes a drain region that serves as a cathode of the light source. The driving circuit is configured to drive the cell. An optical sensor cell and a method for manufacturing thereof are also disclosed.
Metamorphic solar cells
A multijunction solar cell including a metamorphic layer, and particularly the design and specification of the composition, lattice constant, and band gaps of various layers above the metamorphic layer in order to achieve reduction in “bowing” of the semiconductor wafer caused by the lattice mismatch of layers associated with the metamorphic layer.
Avalanche photodiode and method for manufacturing same
A substrate, a first n-type contact layer, a buffer layer, a multiplication layer, an electric field control layer, an absorption layer, and a p-type contact layer are provided. An electrically conductive layer is formed in a central portion of the buffer layer. The substrate is made of a semiconductor having thermal conductivity higher than that of InP, such as SiC, and the first n-type contact layer is made of the same semiconductor as that of the substrate but having n-type conductivity. An n electrode is formed over the first n-type contact layer via a second n-type contact layer.