H01L33/0012

Semiconductor device
10971655 · 2021-04-06 · ·

One embodiment provides a semiconductor device comprising: a substrate; a first semiconductor layer disposed on the substrate; a second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer disposed on the second semiconductor layer; and a reflective layer disposed on the third semiconductor layer, wherein the part between the first and second semiconductor layers, the part between the third and second semiconductor layers, and the second semiconductor layer comprise a depletion region, and the conductivity of the first semiconductor layer and the conductivity of the third semiconductor layer are different from each other, and the second semiconductor layer comprises an intrinsic semiconductor layer.

Fast-switching electro-optic modulators and method of making the same

An electro-optic modulator includes a doped semiconductor crystal having a crystallographic surface having an amplitude modulation orientation, a first metal electrode located on a first surface of the doped semiconductor crystal, a second metal electrode located on a second surface of the doped semiconductor crystal, and accumulation space charge regions located within surface regions of the doped semiconductor crystal that are proximal to the first metal electrode and the second metal electrode and including excess charge carriers of a same type as majority charge carriers of the doped semiconductor crystal.

LIGHT EMITTING DIODE
20210143301 · 2021-05-13 ·

The present disclosure relates to a light emitting diode. The light emitting diode comprises a first semiconductor layer, a second semiconductor layer, an active layer, a first electrode, and a second electrode. The active layer is located between the first semiconductor layer and the second semiconductor layer. The first electrode is a first carbon nanotube, the second electrode is a second carbon nanotube. A first extending direction of the first carbon nanotube and a second extending direction of the second carbon nanotube are crossed with each other. A vertical p-n junction or a vertical p-i-n junction is formed by the first semiconductor layer and the second semiconductor layer in a direction perpendicular to the first semiconductor layer.

SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING ELEMENT
20210135058 · 2021-05-06 ·

A semiconductor light-emitting element includes: an n-type semiconductor layer; an active layer; a p-side contact electrode made of Rh; a p-side electrode covering layer made of Ti or TiN that covers the p-side contact electrode; a first protective layer made of SiO.sub.2 or SiON that covers an upper surface and a side surface of the p-side electrode covering layer in a portion different from that of a first p-side pad opening; a second protective layer made of Al.sub.2O.sub.3 that covers the first protective layer, a side surface of a p-side semiconductor layer, and a side surface of the active layer in a portion different from that of a second p-side pad opening; and a p-side pad electrode that is in contact with the p-side electrode covering layer in the first p-side pad opening and the second p-side pad opening.

Method for producing a device with light emitting and/or light receiving diodes and with self-aligned collimation grid

A method is provided for producing a device with light emitting/light receiving diodes, including: producing, on a substrate, a stack including first and second doped semiconductor layers; first etching of the stack, forming first openings through the entire thickness of the second layer; producing dielectric portions covering, in the first openings, the side walls of the second layer; second etching of the stack, extending the first openings until reaching the substrate, delimiting the p-n junctions of the diodes; etching extending the first openings into a part of the substrate; producing first electrically conductive portions in the first openings, forming first electrodes of the diodes, and producing second electrodes electrically connected to the second layer; and eliminating the substrate, forming a collimation grid.

Optoelectronic device
11862750 · 2024-01-02 · ·

In some embodiments, a semiconductor structure includes a first conductivity type region comprising a first superlattice, and an i-type active region adjacent to the first conductivity type region comprising an i-type superlattice. The first conductivity type region can be a p-type region or an n-type region. The first superlattice can be comprised of a plurality of first unit cells comprising a first set of single crystal layers, and the i-type superlattice can be comprised of a plurality of i-type unit cells comprising a second set of single crystal layers. An average alloy content of the plurality of the first unit cells and the i-type unit cells can be constant along a growth direction. A combined thickness of the second set single crystal layers can be thicker than a combined thickness of the first set of single crystal layers.

Multiple light sources integrated in a neural probe for multi-wavelength activation

Probes include a probe body configured to penetrate biological tissue. High-efficiency light sources are positioned within the probe body. Each high-efficiency light source has a sufficiently intense light output to trigger a light-sensitive reaction in neighboring tissues and has a sufficiently low power output such that a combined heat output of multiple light sources does cause a disruptive temperature increase in the neighboring tissues.

SEMICONDUCTOR LIGHT-EMITTING DEVICE
20200381898 · 2020-12-03 ·

A semiconductor light-emitting device includes a layer structure of a nitride semiconductor, and the layer structure includes an n-type semiconductor layer, a p-type semiconductor layer, and an intermediate layer. The intermediate layer includes an active layer and is provided between the n-type semiconductor layer and the p-type semiconductor layer. The layer structure includes a residual donor in a region at least included in the intermediate layer, the region being situated between the active layer and the p-type semiconductor layer. The intermediate layer includes impurities in the region between the active layer and the p-type semiconductor layer, the impurities compensating the residual donor. Further, the intermediate layer is configured such that a concentration of the impurities in the region between the active layer and the p-type semiconductor layer is higher than a concentration of the impurities in the p-type semiconductor layer.

HIGH-VOLTAGE SOLID-STATE TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS
20200365785 · 2020-11-19 ·

High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.

SEMICONDUCTOR LIGHT-EMITTING DEVICE

A semiconductor light-emitting device includes a substrate; a first semiconductor layer and a second semiconductor layer formed on the substrate, wherein the first semiconductor layer includes a first exposed portion and a second portion; a plurality of first trenches formed on the substrate and including a surface composed by the first exposed portion; a second trench formed on the substrate and including a surface composed by the second exposed portion at a periphery region of the semiconductor light-emitting device, wherein each of the plurality of first trenches is branched from the second trench; and a patterned metal layer formed on the second semiconductor layer and including a first metal region and a second metal region, and portions of the second metal region are formed in the plurality of first trenches and the second trench to electrically connect to the first exposed portion and the second exposed portion.