The present disclosure relates to a method that includes depositing a spalling layer onto a surface that includes a substrate, depositing a device comprising a III-V material onto the spalling layer, resulting in the forming of a stack, and dividing the stack substantially at a plane positioned within the spalling layer to form a first portion that includes the substrate and a second portion that includes the PV device, where the spalling layer includes a first layer configured to provide a compressive stress and a second layer configured to provide a tensile stress, the first layer and the second layer form an interface, the dividing occurs as result of the interface, and the compressive stress and the tensile stress are strain-balanced so that a total strain within the spalling layer is approximately zero.

Disclosed are techniques for manufacturing LEDs. In some examples, a first component is hybrid bonded to a second component through bonding together dielectric materials of the first component and the second component, and then bonding together metal contacts of the first component and the second component. The first component comprises a semiconductor layer stack that includes an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. Prior to hybrid bonding, the first component is subjected to p-side processing, which can involve, among other things, forming a plurality of mesa shapes within the n-side semiconductor layer, the active light emitting layer, and the p-side semiconductor layer. In some examples, n-side processing is performed after the hybrid bonding. The n-side processing can modify a structure or composition of the n-side semiconductor layer, the active light emitting layer, the p-side semiconductor layer, or any combination thereof.

An optoelectronic device is manufactured by an epitaxial growth, on each first layer of many first layers spaced apart from each other on a first support, wherein the first is made of a first semiconductor material, of a second layer made of a second semiconductor material. A further epitaxial growth is made on each second layer of a stack of semiconductor layers. Each stack includes a third layer made of a third semiconductor material in physical contact with the second layer. Each stack is then separated from the first layer by removing the second layer using an etching that is selective simultaneously over both the first and third semiconductor materials. Each stack is then transferred onto a second support. Each of the first and third semiconductor materials is one of a III-V compound or a II-VI compound.

An optical device includes a multilayered GaAs structure including a plurality of sublayers and an optical structure layer on the multilayered GaAs structure, the optical structure layer including a Group III-V compound semiconductor material. The optical structure layer may be, for example, a light-emitting layer having a multi-quantum well structure.

An electronic device may have one or more displays that produce images for a user. The display may include an array of light-emitting diodes. Each light-emitting diode in the array of light-emitting diodes may include a plurality of vias. The vias may be arranged in an array of rows and columns. The light-emitting diodes in the array may share a common cathode. The common cathode may include a conductive layer formed from a reflective material. The conductive layer may be formed in a grid that defines a plurality of openings for the light-emitting diodes or may be formed around the periphery of the array. The array may include light-emitting diodes of two different colors in a head-to-tail arrangement, connected in series, or that share a common cathode. The array may include light-emitting diodes of three different colors that are vertically stacked.

Disclosed herein are techniques for bonding components of LEDs. According to certain embodiments, a device includes a first component and a second component. The first component includes a semiconductor layer stack having an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. The semiconductor layer stack includes a III-V semiconductor material. The second component includes a passive or an active matrix integrated circuit within a Si layer. A first dielectric material of the first component is bonded to a second dielectric material of the second component. First contacts of the first component are aligned with and bonded to second contacts of the second component. The first contacts of the first component form a first pattern within the first dielectric material of the first component, and the second contacts of the second component form a second pattern within the second dielectric material of the second component.

In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface including a flat region having a plurality of three-dimensionally designed surface structures on the flat region, a nucleation layer composed of oxygen-containing AlN in direct contact with the growth surface at the flat region and the three-dimensionally designed surface structures and a nitride-based semiconductor layer sequence on the nucleation layer, wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and wherein the oxygen content in the nucleation layer is greater than 10.sup.19 cm.sup.−3.

A method of forming a Light Emitting Diode (LED) precursor comprising: forming a first semiconducting layer comprising a Group III-nitride on a substrate, selectively removing a portion of the first semiconducting layer to form a mesa structure, and forming a monolithic LED structure. According to the method, the first semiconducting layer has a growth surface on an opposite side of the first semiconducting layer to the substrate. According to the method, the first semiconducting layer is selectively removed to form the mesa structure such that the growth surface of the first semiconducting layer comprises a mesa surface and a bulk semiconducting surface. Further, the monolithic LED structure is formed on the growth surface of the first semiconducting layer such that the monolithic LED structure covers the mesa surface and the bulk semiconducting surface, the monolithic LED structure comprising a plurality of layers, each layer comprising a Group III-nitride, including a second semiconducting layer, an active layer provided on the second semiconducting layer, the active layer configured to generate light, and a p-type semiconducting layer provided on the active layer. A potential barrier is provided between a first portion of the p-type semiconducting layer covering the mesa surface and a second portion of the p-type semiconducting layer covering the bulk semiconducting surface. The potential barrier surrounds the first portion of the p-type semiconducting layer covering the mesa surface.

Disclosed herein are techniques for bonding LED components. According to certain embodiments, a first component including a semiconductor layer stack is hybrid bonded to a second component including a substrate that has a different thermal expansion coefficient than the semiconductor layer stack. The semiconductor layer stack includes an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. The first component and the second component further include first contacts and second contacts, respectively. To hybrid bond the two components, the first contacts are aligned with the second contacts. Then dielectric bonding is performed to bond respective dielectric materials of both components. The dielectric bonding is followed by metal bonding of the contacts, using annealing. To compensate run-out between the first contacts and the second contacts, aspects of the present disclosure relate to changing a curvature of the first component and/or the second component during the annealing stage.

Disclosed herein are techniques for bonding components of LEDs. According to certain embodiments, a method includes performing p-side processing of a first component. The p-side processing is performed from a direction adjacent to a surface of a p-side semiconductor layer of the first component that is opposite to an active light emitting layer of the first component. The method also includes aligning first contacts of the first component with second contacts of the second component, and subsequently performing hybrid bonding of the first component to the second component by performing dielectric bonding of a first dielectric material of the first component with a second dielectric material of the second component at a first temperature, and subsequently performing metal bonding of the first contacts of the first component with the second contacts of the second component by annealing the first contacts and the second contacts at a second temperature.