A light emitting device includes a first active layer on a substrate, a current spreading length, and a plurality of mesa regions on the first active layer. At least a first portion of the first active layer can comprise a first electrical polarity. Each mesa region can include, at least a second portion of the first active layer, a light emitting region on the second portion of the first active layer with a dimension parallel to the substrate smaller than twice the current spreading length, and a second active layer on the light emitting region. The light emitting region can be configured to emit light with a target wavelength from 200 nm to 300 nm. At least a portion of the second active layer can comprise a second electrical polarity.

The invention pertains to the field of nanotechnology. The invention provides highly luminescent nanostructures, particularly highly luminescent nanostructures comprising a ZnSe.sub.1-.sub.xTe.sub.x core and ZnS and/or ZnSe shell layers. The nanostructures comprising a ZnSe.sub.1-.sub.xTe.sub.x core and ZnS and/or ZnSe shell layers display a low full width at half-maximum and a high quantum yield. The invention also provides methods of producing the nanostructures.

The invention pertains to the field of nanotechnology. The invention provides highly luminescent nanostructures, particularly highly luminescent nanostructures comprising a ZnSe.sub.1-.sub.xTe.sub.x core and ZnS and/or ZnSe shell layers. The nanostructures comprising a ZnSe.sub.1-.sub.xTe.sub.x core and ZnS and/or ZnSe shell layers display a low full width at half-maximum and a high quantum yield. The invention also provides methods of producing the nanostructures.

A method of forming a strain relaxation layer in an epitaxial crystalline structure, the method comprising: providing a crystalline template layer comprising a material with a first natural relaxed in-plane lattice parameter; forming a first epitaxial crystalline layer on the crystalline template layer, wherein the first epitaxial crystalline layer has an initial electrical conductivity that is higher than the electrical conductivity of the crystalline template layer; forming a second epitaxial crystalline layer on the first epitaxial crystalline layer, wherein the second epitaxial crystalline layer has an electrical conductivity lower than the initial electrical conductivity of the first epitaxial crystalline layer and comprises a material with a second natural relaxed in-plane lattice parameter that is different to the first natural relaxed in-plane lattice parameter of the crystalline template layer; forming pores in the first epitaxial crystalline layer by electrochemical etching of the first epitaxial crystalline layer to enable strain relaxation in the second epitaxial crystalline layer by plastic deformation of bonds in the first epitaxial crystalline layer and/or at the interface between the first epitaxial crystalline layer and the second epitaxial crystalline layer; and forming one or more channels comprising a conductive material through at least the first epitaxial crystalline layer and the second epitaxial crystalline layer thereby to enable electrical connection to the crystalline template layer through the first epitaxial crystalline layer and the second epitaxial crystalline layer.

A method of forming a strain relaxation layer in an epitaxial crystalline structure, the method comprising: providing a crystalline template layer comprising a material with a first natural relaxed in-plane lattice parameter; forming a first epitaxial crystalline layer on the crystalline template layer, wherein the first epitaxial crystalline layer has an initial electrical conductivity that is higher than the electrical conductivity of the crystalline template layer; forming a second epitaxial crystalline layer on the first epitaxial crystalline layer, wherein the second epitaxial crystalline layer has an electrical conductivity lower than the initial electrical conductivity of the first epitaxial crystalline layer and comprises a material with a second natural relaxed in-plane lattice parameter that is different to the first natural relaxed in-plane lattice parameter of the crystalline template layer; forming pores in the first epitaxial crystalline layer by electrochemical etching of the first epitaxial crystalline layer to enable strain relaxation in the second epitaxial crystalline layer by plastic deformation of bonds in the first epitaxial crystalline layer and/or at the interface between the first epitaxial crystalline layer and the second epitaxial crystalline layer; and forming one or more channels comprising a conductive material through at least the first epitaxial crystalline layer and the second epitaxial crystalline layer thereby to enable electrical connection to the crystalline template layer through the first epitaxial crystalline layer and the second epitaxial crystalline layer.

In a general aspect, a method for growing an InGaN optoelectronic in a reaction chamber, by MOCVD, includes controlling a surface temperature of a wafer to be at least 750° C. during growth of a light-emitting layer. The light emitting layer includes an InGaN quantum well layer having an In % of greater than 25%. The method further includes providing an indium-containing metalorganic precursor and a gallium-containing metalorganic precursor into the reaction chamber and to the wafer during growth of the light-emitting layer when the surface temperature of the wafer is greater than 750° C. The method also includes providing an N-containing species to the wafer at a rate such that a partial pressure of the N-containing species at the surface of the wafer is greater than 1.5 atmospheres during growth of the light-emitting layer of the optoelectronic device when the surface temperature of the wafer is greater than 750° C.

In a general aspect, a method for growing an InGaN optoelectronic in a reaction chamber, by MOCVD, includes controlling a surface temperature of a wafer to be at least 750° C. during growth of a light-emitting layer. The light emitting layer includes an InGaN quantum well layer having an In % of greater than 25%. The method further includes providing an indium-containing metalorganic precursor and a gallium-containing metalorganic precursor into the reaction chamber and to the wafer during growth of the light-emitting layer when the surface temperature of the wafer is greater than 750° C. The method also includes providing an N-containing species to the wafer at a rate such that a partial pressure of the N-containing species at the surface of the wafer is greater than 1.5 atmospheres during growth of the light-emitting layer of the optoelectronic device when the surface temperature of the wafer is greater than 750° C.

A light-emitting structure includes an n-type layer, an active layer, and a p-type layer. The active layer has N quantum well structure periods, each of the N quantum-well structure periods has a well layer and at least one barrier layer. The N quantum-well structure periods include a first light-emitting section and a second light-emitting section. The first light-emitting section is closer to the n-type layer than the second light-emitting section. A method for producing the light-emitting structure, and a light-emitting device that has the light-emitting structure are also disclosed.

A light-emitting structure includes an n-type layer, an active layer, and a p-type layer. The active layer has N quantum well structure periods, each of the N quantum-well structure periods has a well layer and at least one barrier layer. The N quantum-well structure periods include a first light-emitting section and a second light-emitting section. The first light-emitting section is closer to the n-type layer than the second light-emitting section. A method for producing the light-emitting structure, and a light-emitting device that has the light-emitting structure are also disclosed.

A light-emitting device includes a semiconductor epitaxial structure that has a first surface and a second surface opposite to the first surface, and that includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on one another in such order from the first surface to the second surface. The active layer includes a quantum well structure having multiple periodic units each of which includes a well layer and a barrier layer disposed sequentially in such order. A bandgap of the barrier layer is greater than that of the well layer, and the bandgaps of the barrier layers gradually increase in a direction from the first surface of the semiconductor epitaxial structure to the second surface of the semiconductor epitaxial structure.