A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer located over the n-type nitride semiconductor layer and having a V-pit, an active layer located on the V-pit generation layer, and a p-type nitride semiconductor layer located on the active layer. The active layer includes a well layer, which includes a first well layer portion formed along a flat surface of the V-pit generation layer and a second well layer portion formed in the V-pit of the V-pit generation layer. The light emitting diode emits light having at least two peak wavelengths at a single chip level.

A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 μm; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 μm.

A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 μm; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 μm.

A method for making a device. The method comprises forming a buffer layer on a substrate; forming a periodically doped layer on the buffer layer; forming one or more wires on the periodically doped layer, the wires being chosen from nanowires and microwires; and introducing porosity into the periodically doped layer to form a porous distributed Bragg reflector (DBR). Various devices that can be made by the method are also disclosed.

A method for making a device. The method comprises forming a buffer layer on a substrate; forming a periodically doped layer on the buffer layer; forming one or more wires on the periodically doped layer, the wires being chosen from nanowires and microwires; and introducing porosity into the periodically doped layer to form a porous distributed Bragg reflector (DBR). Various devices that can be made by the method are also disclosed.

A quantum device includes a substrate including a first material and including an upper surface thereof, a first layer comprising a compound of the first material disposed on the upper surface of the substrate, a second layer, comprising a metal oxide, disposed on the first layer, a third layer, comprising a noble metal, disposed on the second layer, a fourth layer, comprising a metal oxide, disposed on the third layer, a fifth layer, comprising a piezoelectric material, disposed on the fourth layer, a sixth layer, comprising a noble metal, disposed on the fifth layer, a seventh layer, comprising a material capable of quantum emission, disposed on the sixth layer, and an eighth layer, comprising a noble metal, disposed on the seventh layer, and at least one of the eighth layer and the seventh layer are sized to enable quantum emission from the seventh layer.

An epitaxial structure includes a quantum well structure, a first type semiconductor layer, and a second type semiconductor layer. The quantum well structure has an upper surface and a lower surface opposite to each other and includes at least one quantum well layer and at least one quantum barrier layer stacked alternately. The quantum well layer includes at least one patterned layer, and the patterned layer includes multiple geometric patterns. The first type semiconductor layer is disposed on the lower surface of the quantum well structure. The second type semiconductor layer is disposed on the upper surface of the quantum well structure.

An epitaxial structure includes a quantum well structure, a first type semiconductor layer, and a second type semiconductor layer. The quantum well structure has an upper surface and a lower surface opposite to each other and includes at least one quantum well layer and at least one quantum barrier layer stacked alternately. The quantum well layer includes at least one patterned layer, and the patterned layer includes multiple geometric patterns. The first type semiconductor layer is disposed on the lower surface of the quantum well structure. The second type semiconductor layer is disposed on the upper surface of the quantum well structure.

A vertical light-emitting diode device and a method of fabricating the same are provided. The device may include a conductive substrate serving as a p electrode, a p-type GaN layer provided on the conductive substrate, an active layer provided on the p-type GaN layer, an n-type GaN layer provided on the active layer, an n electrode pattern provided on the n-type GaN layer, a metal oxide structure filling a plurality of holes formed in the n-type GaN layer, and a seed layer provided on bottom surfaces of the holes and used to as a seed in a crystal growth process of the metal oxide structure.

A vertical light-emitting diode device and a method of fabricating the same are provided. The device may include a conductive substrate serving as a p electrode, a p-type GaN layer provided on the conductive substrate, an active layer provided on the p-type GaN layer, an n-type GaN layer provided on the active layer, an n electrode pattern provided on the n-type GaN layer, a metal oxide structure filling a plurality of holes formed in the n-type GaN layer, and a seed layer provided on bottom surfaces of the holes and used to as a seed in a crystal growth process of the metal oxide structure.