Patent classifications
H01L33/405
FLIP-CHIP LIGHT-EMITTING DIODE
A flip-chip light-emitting diode includes an epitaxial structure including a first semiconductor layer, an active layer and a second semiconductor layer that are sequentially disposed on one another in such order. The epitaxial structure is formed with first holes and second holes respectively at a first region and a second region that are independent from each other. Each of the first and second holes extends through the second semiconductor layer and the active layer, and partially exposes the first semiconductor layer. A surface of the first semiconductor layer exposed by the first holes has a total area smaller than a total area of a surface of the first semiconductor layer exposed by the second holes.
NARROWBAND REFLECTOR FOR MICRO-LED ARRAYS
A structure and method of micro-LEDs are described. The micro-LEDs have a GaN semiconductor structure containing a multi-quantum well active region configured to emit light of a visible wavelength range and a multilayer reflector structure that includes a distributed Bragg reflector (DBR) with a maximum reflectance at the visible wavelength range and to reflect the light emitted by the active region towards an emission surface of the semiconductor structure. The multilayer reflector structure also has a protective layer between the DBR and the GaN structure that is transparent to light of visible wavelengths. The multilayer reflector structure also has an absorbing metal layer that absorbs the light of visible wavelengths. A conductive material provides electrically contact to the semiconductor structure.
Radiation-emitting semiconductor chip
In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the radiation-emitting semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the radiation-emitting semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places in plan view of the radiation-emitting semiconductor chip, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer containing a dielectric material, wherein the insulation layer is arranged in places between the connection layer and the current distribution layer.
Optoelectronic semiconductor chip with high reflectivity and method for producing an optoelectronic semiconductor chip with high reflectivity
In one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence with an active zone for generating a radiation. The semiconductor layer sequence is based on AlInGaP and/or on AlInGaAs. A metal mirror for the radiation is located on a rear side of the semiconductor layer sequence opposite a light extraction side. A protective metallization is applied directly to a side of the metal mirror facing away from the semiconductor layer sequence. An adhesion promoting layer is located directly on a side of the metal mirror facing the semiconductor layer sequence. The adhesion promoting layer is an encapsulation layer for the metal mirror, so that the metal mirror is encapsulated at least at one outer edge by the adhesion promoting layer together with the protective metallization.
LIGHT EMITTING ELEMENT AND DISPLAY DEVICE INCLUDING THE SAME
A light emitting element includes a core structure, which includes a first light emitting element core, a second light emitting element core spaced apart from the first light emitting element core, and a first bonding layer between the first light emitting element core and the second light emitting element core, each of the first light emitting element core and the second light emitting element core includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer, and an element active layer between the first semiconductor layer and the second semiconductor layer, and a stacking direction of the first semiconductor layer, the element active layer, and the second semiconductor layer of the first light emitting element core is opposite to a stacking direction of the first semiconductor layer, the element active layer and the second semiconductor layer of the second light emitting element core.
Light-emitting diode structure for improving bonding yield
A light-emitting diode structure for improving bonding yield is provided, which includes a light-emitting diode, a plurality of contact electrodes, an insulating layer structure, and a plurality of bonding electrodes. One surface of the light-emitting diode includes a mesa structure. The contact electrodes are on the mesa structure. The bonding electrodes are on the insulating layer structure and respectively cover at least one contact electrode. A surface of one of the bonding electrodes facing away from the light-emitting diode has a first platform and a second platform. The second platform is on the first platform. A surface area of a vertical projection of the second platform on the light-emitting diode is smaller than that of the first platform on the light-emitting diode, and said vertical projection of the second platform is within that of the first platform.
Electrode structure and semiconductor light-emitting device having a high region part and a low region part
An electrode structure includes: an indium tin oxide (ITO) electrode that includes ITO; an Al electrode that includes Al and covers the ITO electrode; and a barrier electrode that includes at least one of TiN and Cr and is interposed in a region between the ITO electrode and the Al electrode.
VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.
OPTICAL PROJECTION DEVICE HAVING A GRID STRUCTURE
An optical projection device and a method of producing the optical projection device are described. The optical projection device includes: a plurality of LEDs (light-emitting diodes), the LEDs each including a semiconductor mesa laterally spaced apart from one another by a grid structure. Each of the semiconductor mesas includes an n-type material and a p-type material adjoining at least partly the n-type material. The grid structure at least partly laterally surrounds at least the n-type material of each of the semiconductor mesas. The grid structure includes a conductive material that electrically interconnects the n-type material of the semiconductor mesas. The grid structure is configured to block optical crosstalk between light emitted by the LEDs.
Light-emitting device
A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.