A semiconductor structure includes a substrate, at least one first gate structure, at least one source drain structure, at least one bottom conductor, and a first dielectric layer. The first gate structure is present on the substrate. The source drain structure is present on the substrate. The bottom conductor is electrically connected to the source drain structure. The bottom conductor has an upper portion and a lower portion between the upper portion and the source drain structure, and a gap is at least present between the upper portion of the bottom conductor and the first gate structure. The first dielectric layer is at least present between the lower portion of the bottom conductor and the first gate structure.

A method includes forming a first conductive line and a second conductive line in a dielectric layer, etching a portion of the dielectric layer to form a trench between the first conductive line and the second conductive line, and forming a first etch stop layer. The first etch stop layer extends into the trench. A second etch stop layer is formed over the first etch stop layer. The second etch stop layer extends into the trench, and the second etch stop layer is more conformal than the first etch stop layer. A dielectric material is filled into the trench and over the second etch stop layer. An air gap is formed in the dielectric material.

An interconnection structure includes a non-insulator structure, a dielectric structure, and a conductive structure. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The trench opening has a bottom surface and at least one recess in the bottom surface. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The conductive structure is at least separated from the bottom of the recess.

The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

A memory structure is described, which includes a substrate, a word line structure, a bit line contact, and a bit line. The substrate has a trench. The word line structure is disposed in the trench of the substrate. The word line structure includes a word line, a gate dielectric layer, and a capping layer. The word line is disposed in the trench. The gate dielectric layer is disposed between the word line and the substrate. The capping layer covers the word line. The capping layer includes a first material film, and a dielectric constant of the first material layer is smaller than a dielectric constant of silicon nitride. The bit line contact is disposed on a portion of the trench and a portion of the capping layer. The bit line is disposed over the bit line contact and electrically connected to the bit line contact.

The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

A memory structure is described, which includes a substrate, a word line structure, a bit line contact, and a bit line. The substrate has a trench. The word line structure is disposed in the trench of the substrate. The word line structure includes a word line, a gate dielectric layer, and a capping layer. The word line is disposed in the trench. The gate dielectric layer is disposed between the word line and the substrate. The capping layer covers the word line. The capping layer includes a first material film, and a dielectric constant of the first material layer is smaller than a dielectric constant of silicon nitride. The bit line contact is disposed on a portion of the trench and a portion of the capping layer. The bit line is disposed over the bit line contact and electrically connected to the bit line contact.

Embodiments provide a semiconductor structure and a fabricating method. The semiconductor structure includes: a substrate, where a trench is formed in the substrate; a conductive layer positioned in the trench, where the conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer is positioned on the first conductive layer, and a projection area of a bottom of the second conductive layer within the trench is greater than a projection area of a top of the first conductive layer within the trench; a dielectric layer positioned between the conductive layer and an inner wall of the trench, where a top of the dielectric layer is lower than the top of the first conductive layer; an isolation layer positioned on the conductive layer; and a void defined by the isolation layer, the conductive layer, the dielectric layer, and a side wall of the trench.