A wafer-level buffer layer is disclosed. The wafer-level buffer layer is configured to prevent cracking and chipping the back-end-of-line (BEOL) dielectric during wafer singulation process. The wafer-level buffer layer is a composite wafer-level buffer layer with a vibration damping agent. The vibration damping agent includes a polymer-based base layer with fillers. The damping agent absorbs or dampens the vibration of the saw blade during dicing to prevent cracking and chipping of the BEOL dielectric.

The present disclosure relates to a method for forming an integrated chip. The method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. The method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. The method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.

A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. This prevents die cracking, for example during backgrind of the wafer. Moreover, the absence of laser grooves along the short edges of the semiconductor dies prevents die cracking, for example along short edges of dies overhanging empty space that are stressed during portions of the packaging process.

A photo alignment structure is provided that includes a wafer having scribe lines defined therein in a top planar surface of the wafer. An alignment structure is disposed on a top planar surface of the wafer longitudinally aligned with a portion of selected scribe lines, where the alignment structure is comprised of metal layers. A slot is defined along a longitudinal axis of the alignment structure in at least one of the metal layers.

The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess.

An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

In certain embodiments, a method for designing a semiconductor device includes generating a two-dimensional design for fabricating chiplets on a semiconductor substrate. The chiplets are component levels for a multi-chip integrated circuit. The two-dimensional design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The second chiplet is adjacent to the first chiplet on the semiconductor substrate. The second layout is a mirror image of the first layout across a reference line shared by the first chiplet and the second chiplet. The first surface of the first chiplet and the first surface of the second chiplet are both either top surfaces or bottom surfaces. The method further includes generating a photomask according to the design.

A method for manufacturing a display device is provided. A process of forming an inspection pattern, in which a protective film unit is partially removed in a thickness direction, in a pad area portion of the protective film unit, which corresponds to a pad area of a display unit, may be performed, and then, a process of delaminating the pad area portion of the protective film unit may be performed. A process of checking whether the inspection pattern exists may be performed to check whether the delamination has succeeded, and, at the same time, a process of measuring distances from an alignment mark to each of a long side and a short side of the display unit may be performed.