A module includes a substrate, a component mounted on a top surface that is one principal surface of the substrate, a first shielding film provided on a top surface and a side surface of the component, a sealing resin provided on the top surface of the substrate and seals the component, and a second shielding film provided on a top surface of the sealing resin. A hole is provided on a top surface of the sealing resin, to reach at least a part of the first shielding film. The second shielding film disposed in the hole is brought into contact with the first shielding film at positions facing a top surface and a side surface of the component.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

An electronic device includes a via-array substrate, an outer layer, and an alignment substrate. The via-array substrate has a plurality of first vias. The outer layer has a plurality of second vias and is disposed on a side of the via-array substrate. The first vias are greater in distribution density or quantity than the second vias. A part of the first vias is electrically connected to the second vias, and another part of the first vias is electrically floating. The alignment substrate includes a core layer disposed on the outer layer, a plurality of conductive traces, a plurality of interconnecting pads, and a plurality of alignment mark pads. The conductive traces are disposed in the core layer. The interconnecting pads and the alignment mark pads are disposed on a surface of the core layer located away from the outer layer. A part of the conductive traces electrically connects a part of the interconnecting pads and a part of the first vias. A pattern of each of the alignment mark pads is different from a pattern of each of the interconnecting pads.

A semiconductor module includes a semiconductor element, a case configured to house the semiconductor element, and a plurality of control terminal units. Each of the control terminal units includes at least one control terminal electrically connected to the semiconductor element, and a guide block constituted of a separate component from the case fixed integrally to the at least one control terminal. The at least one control terminal each includes a terminal pin part protruding from an outer wall surface of the case. Each of the guide blocks includes a guide pin part protruding from the outer wall surface of the case in a direction the same as the direction in which the terminal pin part protrudes. The guide blocks of the control terminal units are constituted of separate components.

A semiconductor device, including a semiconductor element; a case having a frame portion, which has an inner periphery that surrounds a housing space for accommodating the semiconductor element; and a lid covering the housing space. The inner periphery of the frame portion has a stepped portion formed thereon, the stepped portion including a step supporting surface positioned at a level lower than a front surface of the frame portion and being approximately parallel to the front surface of the frame portion. The lid has a lateral surface surrounding the lid, and a front surface and a bottom surface approximately parallel to the step supporting surface. The lid has a reservoir formed in the front surface thereof and extending from the lateral surface, the reservoir having a reservoir surface positioned at a level lower than the front surface of the lid.

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

A semiconductor device includes a package, a control terminal group including at least three control terminals inputting a control signal to a semiconductor element and projecting from a side surface of a first side out of the first side and a second side opposite to the first side of the package, and a main terminal group including at least three main terminals energizing the semiconductor element with a main current and projecting from a side surface of the second side. Middle portions of the two respective terminals of the control terminal group and the main terminal group are provided with stoppers for preventing over-insertion into the substrate. A middle portion of at least one terminal of at least any one of the terminal groups of the control terminal group and the main terminal group is provided with stoppers for identifying a rated current of the semiconductor device.

A semiconductor device includes a conductive support member, a control element, an insulating element, a driver element and a sealing resin. The conductive support member includes a first lead and a second lead. The first lead has a first pad portion. The second lead has a second pad portion. The second pad portion is adjacent to the first pad portion in a first direction perpendicular to a thickness direction of the first pad portion. The control element is mounted on the first pad portion. The insulating element is mounted on the first pad portion and electrically connected to the control element. The driver element is mounted on the second pad portion and electrically connected to the insulating element. The sealing resin covers the first pad portion, the second pad portion, the control element, the insulating element and the driver element. As viewed in the thickness direction, the first pad portion has a first edge adjacent to the second pad portion in the first direction and extending in a second direction perpendicular to the thickness direction and the first direction. The first edge has a first end and a second end opposite in the second direction. As viewed in the thickness direction, the second pad portion has a second edge adjacent to the first edge in the first direction and extending in the second direction. The second edge has a third end and a fourth end opposite in the second direction. One of the third end and the fourth end is located between the first end and the second end in the second direction.

The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.

[PROBLEM] In accordance with one aspect of the present invention, to provide a tape and a sheet that make it possible to reduce cracking that would otherwise occur at the chip side face during dicing.

[SOLUTION MEANS] One aspect of the present invention relates to a sheet. The sheet comprises dicing film. The dicing film comprises a base layer and an adhesive layer disposed on the base layer. The sheet further comprises a semiconductor backside protective film disposed on the adhesive layer. Shear adhesive strength at 25° C. of the semiconductor backside protective film with respect to a silicon chip is not less than 1.7 kgf/mm.sup.2.