Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.

A chip on film package structure including a flexible film, a patterned metal layer, a chip, a patterned solder resist layer, and a code-included pattern is provided. The flexible film comprises a chip mounting region and a peripheral region surrounding the chip mounting region. The patterned metal layer disposed on the flexible film. The chip mounted on the chip mounting region and electrically connected to the patterned metal layer. The patterned solder resist layer exposing the chip mounting region and covering a part of the patterned metal layer. The code-included pattern disposed on the peripheral region of the flexible film. The code-included pattern comprises a plurality of machine-readable data. A method for reading a code-included pattern on a package structure is also provided.

A semiconductor device, including a board, a semiconductor module disposed on a front surface of the board, and a case that includes (1) side wall portions that are disposed on the front surface of the board and that surround, with the board, a storage area including the semiconductor module, (2) a cover portion that is disposed on the side wall portions to cover the storage area, the cover portion having a terminal opening formed therein, and (3) a guiding projection portion formed on an inner surface of the cover portion, and protruding toward the storage area. The semiconductor device further includes sealing material with which the storage area is filled and which seals the semiconductor module. The guiding projection portion has a projecting end portion that is in contact with the sealing material.

A bonding device measures a position deviation amount of the chip with respect to the substrate in a state where the chip and the substrate are in contact, and corrects and moves the chip relatively to the substrate in such a way as to reduce the position deviation amount, based on the measured position deviation amount. Then, the bonding device fixes the chip to the substrate by irradiating a resin portion of the chip with an ultraviolet ray and curing the resin portion when the position deviation amount of the chip with respect to the substrate is equal to or less than a position deviation amount threshold value.

A chip transfer method including: disposing a target substrate in a closed cavity, the target substrate including a first alignment bonding structure and a second alignment bonding structure; applying a charge of a first polarity to the first alignment bonding structure of the target substrate; applying a charge of a second polarity to a first chip bonding structure of a chip; injecting an insulating fluid into the closed cavity to suspend the chip in the insulating fluid within the closed cavity; and applying a bonding force to the chip.

A method for transferring a plurality of die operatively associated with a transfer apparatus to a glass substrate to form a circuit component. The transfer occurs by positioning the glass substrate to face a first surface of a die carrier carrying multiple die. A reciprocating transfer member thrusts against a second surface of the die carrier to actuate the transfer member thereby causing a localized deflection of the die carrier in a direction of the surface of the glass substrate to position an initial die proximate to the glass substrate. The initial die transfers directly to a circuit trace on the glass substrate. At least one of the die carrier or the transfer member is then shifted such that the transfer member aligns with a subsequent die on the first surface of the die carrier. The acts of actuating, transferring, and shifting are repeated to effectuate a transfer of the multiple die onto the glass substrate.

According to one embodiment, a display device includes a display panel including a first substrate, and a wiring board mounted on a mounting portion of the first substrate. The display panel includes a first terminal and a second terminal located in the mounting portion, a first alignment mark located in the mounting portion and located between the first terminal and the second terminal, a first wiring line connected to the first terminal, and a second wiring line connected to the second terminal. The wiring board includes a first connection wiring line connected to the first terminal, a second connection wiring line connected to the second terminal, and a second alignment mark located between the first connection wiring line and the second connection wiring line.

A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.