A method of marking information on a substrate for use in a semiconductor component is provided. The method comprises providing a substrate for use in a semiconductor component, providing a metal layer on a surface of the substrate, and providing a marking within the metal layer. A method of making a die, a radio-frequency module and a wireless mobile device; as well as a substrate, a die, a radio-frequency module and a wireless mobile device is also provided.

A current-sensing system includes a conductor for carrying a first electrical current generating a first magnetic field. A device, spaced from the conductor by a clearance, includes a semiconductor integrated circuit die in a package. The semiconductor integrated circuit die includes at least one elongated bar of a first ferromagnetic material magnetized by the first magnetic field; a sensor comprising a first coil wrapped around the at least one elongated bar to sense the bar's magnetization; and an electronic driver creating a second electrical current flowing through a second coil wrapped around the at least one elongated bar generating a second magnetic field to compensate the at least one bar's magnetization. The package has a first outer surface free of device terminals. A discrete plate of a second ferromagnetic material is positioned in the clearance and is conformal with the first outer surface of the package.

A conductive composition is provided that can be spray coated to form a shielding layer having good shielding capability against 100 MHz to 40 GHz electromagnetic waves, and having desirable adhesion to a package with good laser mark visibility. A method of production of a shielded package with such a conductive composition is also provided. A conductive composition includes at least: (A) a (meth)acrylic resin having a weight average molecular weight of 1,000 or more and 400,000 or less; (B) a monomer having a glycidyl group and/or a (meth)acryloyl group within the molecule; (C) a granular resin component having an average particle diameter of 10 nm to 700 nm; (D) a conductive filler having an average particle diameter of 10 to 500 nm; (E) a scale-like conductive filler having an average particle diameter of 1 to 50 μm; (F) a radical polymerization initiator; and (G) an epoxy resin curing agent, the granular resin component (C) being present in a proportion of 3 to 27 mass % in a resin component containing the acrylic resin (A), the monomer (B), and the granular resin component (C), the conductive filler (D) and the conductive filler (E) being present in an amount of 2,000 to 12,000 parts by mass in total relative to 100 parts by mass of the resin component, the radical polymerization initiator (F) being present in an amount of 0.5 to 40 parts by mass relative to 100 parts by mass of the resin component, and the epoxy resin curing agent (G) being present in an amount of 0.5 to 40 parts by mass relative to 100 parts by mass of the resin component.

According to an embodiment of the present invention, an electronic assembly comprises: a circuit board including a plurality of connection parts having electrical conductivity; a plurality of spaced apart semiconductor integrated circuits mounted on the circuit board and electrically connected to the plurality of connection parts; a protective layer disposed on the plurality of semiconductor integrated circuits, substantially surrounding the semiconductor integrated circuits, and having a flat upper surface; and a heat spreading copper layer disposed on the protective layer, having an average thickness greater than or equal to about 3 microns, and an average grain size greater than about 0.15 micron, wherein the heat spreading copper layer may occupy substantially the same space in a length and a width as the circuit board (coextensive), and the average thickness of the protective layer may be equal to or greater than the height of the plurality of spaced apart semiconductor integrated circuits.

A semiconductor packaging substrate is provided, which includes a build-up circuit structure, at least one fiducial marker structure, and an insulating protective layer. The fiducial marker structure includes a fiducial marker and a second insulating layer covering the fiducial marker. The second insulating layer is made of a transparent insulation material, so that the fiducial marker inside the second insulating layer can be seen through a CCD lens or tool maker microscope for alignment so as to easily create a smaller see-through area and the process parameters can be easily controlled. Besides, the disclosure further provides a manufacturing method for the semiconductor packaging substrate.

Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Provided is a color image sensor including: a silicon semiconductor chip housed in a package and having a plurality of pixels; an optical glass formed on an upper portion of the silicon semiconductor chip and having a color filter pattern formed thereon; and a window glass formed on the optical glass. According to embodiments of the present invention, color interference between neighboring pixels can be minimized, and the size of the silicon semiconductor chip can be designed smaller under the same color separation condition, which is economical.

Provided is a display panel, including a through hole, an isolation area, and a display area. The isolation area is around the through hole. The isolation area is between the through hole and the display area. The isolation area includes at least two graphic marks for detecting the hole accuracy of the through hole. The at least two graphic marks are spaced apart from each other around the through holes. Graphic marks are arranged in an isolation area of a display panel. The isolation area is between a through hole and a display area. That is, the graphic marks are around the through hole.

Embodiments disclosed herein include semiconductor devices. In an embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment a fiducial is on the substrate. In an embodiment, the fiducial is a cantilever beam that extends out past an edge of the substrate.

A semiconductor package may include a board, a first semiconductor chip mounted on the board, and a plurality of second semiconductor chips stacked on the first semiconductor chip. The board may include alignment marks on a top surface of the board and which are arranged in spaced apart relationship along a first direction. Each alignment mark includes a first side surface parallel to the first direction and a second side surface parallel to a second direction perpendicular to the first direction. A coupling pad is on the top surface of the board and between adjacent ones of the alignment marks. The first side surfaces may be collinear in the first direction. Each of the second semiconductor chips may include end surfaces, which are parallel to the second direction and are collinear with respective second side surfaces in the second direction.