A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure.

A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.

In one embodiment, a power module device includes a base plate, an electrically insulating ceramic layer on the base plate, and an electrically insulating first insulating layer on the ceramic layer. The first insulating layer includes a prepreg material. An electrically conductive lead frame is disposed on the first insulating layer and electrically insulated therefrom. A power semiconductor device disposed on the lead frame and embedded between the lead frame and a second insulating layer.

In one embodiment, a power module device includes a base plate, an electrically insulating ceramic layer on the base plate, and an electrically insulating first insulating layer on the ceramic layer. The first insulating layer includes a prepreg material. An electrically conductive lead frame is disposed on the first insulating layer and electrically insulated therefrom. A power semiconductor device disposed on the lead frame and embedded between the lead frame and a second insulating layer.

A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.

A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.