Patent classifications
H01L2224/831
Placement method for circuit carrier and circuit carrier
The invention concerns a process for the production of a circuit carrier (1) equipped with at least one surface-mount LED (SMD-LED), wherein the at least one SMD-LED (2) is positioned in oriented relationship to one or more reference points (3) of the circuit carrier (1) on the circuit carrier (1), wherein the position of a light-emitting region (4) of the at least one SMD-LED (2) is optically detected in the SMD-LED (2) and the a least one SMD-LED (2) is mounted to the circuit carrier (1) in dependence on the detected position of the light-emitting region (4) of the at least one SMD-LED (2), and such a circuit carrier (1).
Apparatus and method for securing substrates with varying coefficients of thermal expansion
An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.
Method of forming semiconductor device package having testing pads on a topmost die
In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
Method of forming semiconductor device package having testing pads on a topmost die
In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR CHIPS
A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR CHIPS
A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
CONTROL OF UNDER-FILL USING AN ENCAPSULANT AND A TRENCH OR DAM FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE
Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use an encapsulant on solder balls in combination with a dam or a trench to control the distribution of an under-fill material between one or more components and a packaging substrate. The encapsulant can be used in the ball attach process. The fluxing agent leaves behind a material that encapsulates the base of each solder ball. The encapsulant reduces the tendency of the under-fill material to wick around the solder balls by capillary action which can prevent or limit the capillary under-fill material from flowing onto or contacting other components. The dam or trench aids in retaining the under-fill material within a keep out zone to prevent or limit the under-fill material from contacting other components.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.
Patterning Polymer Layer to Reduce Stress
A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.