H01L2924/01327

METAL PARTICLE, PASTE, FORMED ARTICLE, AND LAMINATED ARTICLE
20170282302 · 2017-10-05 ·

Aiming at providing a metal particle, an electro-conductive paste, a formed article, and a laminated article that are able to form a highly reliable and high-quality electric interconnect, an electro-conductive bonding portion, or a three-dimensional structure that is less likely to produce the Kirkendall void, this invention discloses a metal particle which include an outer shell and a core part, the outer shell including an intermetallic compound and covering the core part.

Semiconductor device

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

Semiconductor chip metal alloy thermal interface material

Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.

Semiconductor chip metal alloy thermal interface material

Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.

BONDING STRUCTURE, BONDING MATERIAL AND BONDING METHOD
20170232562 · 2017-08-17 · ·

A bonding structure bonds a Cu wiring line and a device electrode with each other. The bonding structure is arranged between the Cu wiring line and the device electrode, and comprises a first intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the Cu wiring line, a second intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the device electrode, and an intermediate layer that is present between the intermetallic compound layers. In the intermediate layer, a network-like IMC (a network-like intermetallic compound of Cu and Sn) is present in Sn.

MANUFACTURING METHOD OF PACKAGE

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

MANUFACTURING METHOD OF PACKAGE

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

Method of transferring and bonding an array of micro devices

Electrostatic transfer head array assemblies and methods of transferring and bonding an array of micro devices to a receiving substrate are described. In an embodiment, a method includes picking up an array of micro devices from a carrier substrate with an electrostatic transfer head assembly supporting an array of electrostatic transfer heads, contacting a receiving substrate with the array of micro devices, transferring energy from the electrostatic transfer head assembly to bond the array of micro devices to the receiving substrate, and releasing the array of micro devices onto the receiving substrate.

Method of transferring and bonding an array of micro devices

Electrostatic transfer head array assemblies and methods of transferring and bonding an array of micro devices to a receiving substrate are described. In an embodiment, a method includes picking up an array of micro devices from a carrier substrate with an electrostatic transfer head assembly supporting an array of electrostatic transfer heads, contacting a receiving substrate with the array of micro devices, transferring energy from the electrostatic transfer head assembly to bond the array of micro devices to the receiving substrate, and releasing the array of micro devices onto the receiving substrate.

Paste for joining components of electronic modules, system and method for applying the paste

The invention relates to a paste, preferably for joining components of power electronics modules, the paste comprising a solder powder, a metal powder and a binder, wherein the binder binds solder powder and metal powder before a first heating. According to the invention, the binder is free of flux or is a flux having only low activation. In this way, a joining layer which exhibits only few included voids and good mechanical and electrical stability can be provided between a first and a second component.