A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.

A joint structure, in which an electronic component and a wiring substrate are joined to each other, includes: a first layer being provided on one side of the electronic component and the wiring substrate, and being composed of a first metal containing Sn; a second layer being provided on the other side of the electronic component and the wiring substrate, and being composed of a second metal that forms an intermetallic compound with Sn; and a third layer being provided at a joint interface between the first layer and the second layer, and being composed of an intermetallic compound of the first metal and the second metal. An average thickness of the third layer is 0.1 μm or more to 0.5 μm or less.

A stacked MLCC capacitor is provided wherein the capacitor stack comprises multilayered ceramic capacitors wherein each multilayered ceramic capacitor comprises first electrodes and second electrodes in an alternating stack with a dielectric between each first electrode and each adjacent second electrode. The first electrodes terminate at a first side and the second electrodes second side. A first transient liquid phase sintering conductive layer is the first side and in electrical contact with each first electrode; and a second transient liquid phase sintering conductive layer is on the second side and in electrical contact with each second electrode.

A stacked MLCC capacitor is provided wherein the capacitor stack comprises multilayered ceramic capacitors wherein each multilayered ceramic capacitor comprises first electrodes and second electrodes in an alternating stack with a dielectric between each first electrode and each adjacent second electrode. The first electrodes terminate at a first side and the second electrodes second side. A first transient liquid phase sintering conductive layer is the first side and in electrical contact with each first electrode; and a second transient liquid phase sintering conductive layer is on the second side and in electrical contact with each second electrode.

A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.

A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.

The present disclosure provides a method of fabricating a semiconductor device. The method can include bonding a first die and a second die face to face, the first die including a substrate, transistors formed on a face side of the first die over a semiconductor layer with an insulating layer between the substrate and the semiconductor layer, and a first contact structure on the face side of the first die extending through the insulating layer. The method can also include exposing the first contact structure from the back side of the first die, forming, from the back side of the first die, a contact hole in the insulating layer to expose the semiconductor layer, and forming, on the back side of the first die, a first pad-out structure connected with the first contact structure and a second pad-out structure, on the contact hole, conductively connected with the semiconductor layer.