An electronic-part-reinforcing thermosetting resin composition has: a viscosity of 5 Pa.Math.s or less at 140° C.; a temperature of 150° C. to 170° C. as a temperature corresponding to a maximum peak of an exothermic curve representing a curing reaction; and a difference of 20° C. or less between the temperature corresponding to the maximum peak and a temperature corresponding to one half of the height of the maximum peak in a temperature rising range of the exothermic curve.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

According to one embodiment, a semiconductor device includes a first substrate, a second substrate joined to the first substrate. A first region of the semiconductor device that includes a peripheral circuit is between the first substrate and the second substrate. A second region that includes a memory cell array is between the first region and the second substrate. A layer that is embedded in the second substrate has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide.

A light-emitting device includes a carrier, a light-emitting element and a connection structure. The carrier includes a first electrical conduction portion. The light-emitting element includes a first light-emitting layer capable of emitting first light and a first contact electrode formed under the light-emitting layer. The first contact electrode is corresponded to the first electrical conduction portion. The connection structure includes a first electrical connection portion and a protective portion surrounding the first contact electrode and the first electrical connection portion. The first electrical connection portion includes an upper portion, a lower portion and a neck portion arranged between the upper portion and the lower portion. An edge of the upper portion is protruded beyond the neck portion, and an edge of the lower portion is protruded beyond the upper portion.

A light-emitting device includes a carrier, a light-emitting element and a connection structure. The carrier includes a first electrical conduction portion. The light-emitting element includes a first light-emitting layer capable of emitting first light and a first contact electrode formed under the light-emitting layer. The first contact electrode is corresponded to the first electrical conduction portion. The connection structure includes a first electrical connection portion and a protective portion surrounding the first contact electrode and the first electrical connection portion. The first electrical connection portion includes an upper portion, a lower portion and a neck portion arranged between the upper portion and the lower portion. An edge of the upper portion is protruded beyond the neck portion, and an edge of the lower portion is protruded beyond the upper portion.

The purpose of the present invention is to provide an adhesive composition which allows an alignment mark to be recognized, ensures sufficient solder wettability of a joining section, and is excellent in suppression of void generation. The adhesive composition includes: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average, particle diameter of 30 to 200 nm, the flux (C) containing an acid-modified rosin.

The purpose of the present invention is to provide an adhesive composition which allows an alignment mark to be recognized, ensures sufficient solder wettability of a joining section, and is excellent in suppression of void generation. The adhesive composition includes: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average, particle diameter of 30 to 200 nm, the flux (C) containing an acid-modified rosin.