An anisotropic conductive film manufacturing method capable of reducing manufacturing costs. Also, an anisotropic conductive film capable of suppressing the occurrence of conduction defects. The anisotropic conductive film manufacturing method includes: a holding step of supplying conductive particles having a plurality of particle diameters on a member having a plurality of opening parts, and holding the conductive particles in the opening parts; and a transfer step of transferring the conductive particles held in the opening parts to an adhesive film. In the particle diameter distribution graph (X-axis: particle diameter (μm), Y-axis: number of particles) of the conductive particles held in the opening parts, the shape of the graph is such that the slope is substantially infinite in a range at or above a maximum peak particle diameter.

An anisotropic conductive film manufacturing method capable of reducing manufacturing costs. Also, an anisotropic conductive film capable of suppressing the occurrence of conduction defects. The anisotropic conductive film manufacturing method includes: a holding step of supplying conductive particles having a plurality of particle diameters on a member having a plurality of opening parts, and holding the conductive particles in the opening parts; and a transfer step of transferring the conductive particles held in the opening parts to an adhesive film. In the particle diameter distribution graph (X-axis: particle diameter (μm), Y-axis: number of particles) of the conductive particles held in the opening parts, the shape of the graph is such that the slope is substantially infinite in a range at or above a maximum peak particle diameter.

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.

A film-shaped firing material (1) is provided, including first metal particles (10), second metal particles (20), and a binder component (30), in which the average particle diameter of the first metal particles (10) is 100 nm or less, and the maximum particle diameter thereof is 250 nm or less, the average particle diameter of the second metal particles (20) is in a range of 1000 to 7000 nm, the minimum particle diameter thereof is greater than 250 nm, and the maximum particle diameter thereof is 10000 nm or less, and the mass ratio of the first metal particles to the second metal particles is 0.1 or greater.

A film-shaped firing material (1) is provided, including first metal particles (10), second metal particles (20), and a binder component (30), in which the average particle diameter of the first metal particles (10) is 100 nm or less, and the maximum particle diameter thereof is 250 nm or less, the average particle diameter of the second metal particles (20) is in a range of 1000 to 7000 nm, the minimum particle diameter thereof is greater than 250 nm, and the maximum particle diameter thereof is 10000 nm or less, and the mass ratio of the first metal particles to the second metal particles is 0.1 or greater.

Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.

Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.