An electronic element mounting substrate includes a first insulating layer, a second insulating layer, a first metal layer, and a through-hole conductor. The first insulating layer and the second insulating layer are aligned in a first direction. The first metal layer is positioned between the first insulating layer and the second insulating layer. The through-hole conductor extends in the first direction from the first insulating layer through the second insulating layer. The first metal layer includes a first portion positioned away from the through-hole conductor and a second portion in contact with the through-hole conductor. The second portion has a larger thickness than the first portion.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material.

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material.

An optoelectronic semiconductor component includes a carrier and at least one optoelectronic semiconductor chip mounted on the carrier top. The semiconductor component includes at least one bonding wire, via which the semiconductor chip is electrically contacted, and at least one covering body mounted on a main radiation side and projects beyond the bonding wire. At least one reflective potting compound encloses the semiconductor chip laterally and extends at least as far as the main radiation side of the semiconductor chip. The bonding wire is covered completely by the reflective potting compound or completely by the reflective potting compound together with the covering body.

A power module includes: an insulating layer; a first metallic plate disposed on the insulating layer; a first semiconductor chip disposed on the first metallic plate; a first adhesive insulating layer and a second adhesive insulating layer disposed on the first metallic plate; a first metallic land for main electrode wiring disposed on the first adhesive insulating layer; and a first metallic land for signal wiring disposed on the second adhesive insulating layer. There can be provided a power module having reduced cost, reduced warpage of the whole of a substrate, stabilized quality, and improved reliability; and a fabrication method for such a power module.

The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

Methods and compositions are described for controlling bond line thickness of a joint formed during sintering. Spacer particles of a predetermined particle type and size are added in a predetermined concentration to a sintering paste to form a sintering paste mixture prior to sintering to achieve a targeted bond line thickness during sintering. The sintering paste mixture can be sintered under pressure and pressure-less process conditions. Under pressured sintering, the amount of pressure applied during sintering may be adjusted depending on the composition and concentration of the spacer particles to adjust bond line thickness.

Methods and compositions are described for controlling bond line thickness of a joint formed during sintering. Spacer particles of a predetermined particle type and size are added in a predetermined concentration to a sintering paste to form a sintering paste mixture prior to sintering to achieve a targeted bond line thickness during sintering. The sintering paste mixture can be sintered under pressure and pressure-less process conditions. Under pressured sintering, the amount of pressure applied during sintering may be adjusted depending on the composition and concentration of the spacer particles to adjust bond line thickness.

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.