A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at least one separation region in the semiconductor substrate between a first region and a second region of the semiconductor substrate, arranging the semiconductor substrate on a breaking device, wherein the breaking device comprises a breaking edge, and wherein the semiconductor substrate is arranged with the film facing the breaking device and in at least one alignment position with the at least one separation region aligned with the breaking edge, and forcing the semiconductor substrate to bend the first region with respect to the second region over the breaking edge until the film separates between the breaking edge and the at least one separation region.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

A composite substrate includes a submount substrate of an alternating pattern of electrically insulative portions, pieces, layers or segments and electrically conductive portions, pieces, layers or segments, and a shaft, back or plate for supporting the alternating pattern of electrically insulative portions and electrically conductive portions. An active device having a P-N junction can be mounted on the submount substrate. The electrically insulative portions, pieces, layers or segments can be formed from diamond while the electrically conductive portions, pieces, layers or segments can be formed from a metal or metal alloy.

A composite substrate includes a submount substrate of an alternating pattern of electrically insulative portions, pieces, layers or segments and electrically conductive portions, pieces, layers or segments, and a shaft, back or plate for supporting the alternating pattern of electrically insulative portions and electrically conductive portions. An active device having a P-N junction can be mounted on the submount substrate. The electrically insulative portions, pieces, layers or segments can be formed from diamond while the electrically conductive portions, pieces, layers or segments can be formed from a metal or metal alloy.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.