Provided is a semiconductor package including a first redistribution layer, a semiconductor device on the first redistribution layer, a substrate protection layer below the first redistribution layer, a groove in a bottom surface of the substrate protection layer, a passive device in the groove, an underfill between the passive device and the groove, and a dam apart from the passive device, the dam protruding from the substrate protection layer and at least partially surrounding the passive device.

A disclosed system includes a package body that includes a system-on-a-chip (SoC) and an interconnect region. In an embodiment, the interconnect region includes a first conductive path between the SoC and a voltage regulator module (VRM), a second conductive path between the SoC and a first external connection, and a third conductive path between the VRM and a second external connection. In another embodiment, the VRM is positioned between and coupled to a first portion of the SoC and a first surface of the interconnect region. A second portion of the SoC is coupled directly to the first surface of the interconnection region. In another embodiment, the interconnect region has first and second opposing surfaces. The SoC is positioned on the first surface of the interconnect region. The VRM is externally coupled to a first surface of the package body adjacent to the second surface of the interconnect region.

In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

A chip package, an electronic device, and methods for fabricating the same are disclosed herein. In one example, a chip package includes a package substrate, an integrated circuit (IC) die, and a stiffener. The IC die has a first height and is mounted on a top surface of the package substrate. The stiffener is mounted to the top surface of the package substrate. A cavity is disposed in the stiffener. The cavity has an opening formed through the stiffener that faces towards the IC die.

A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, and an upper substrate arranged on an upper surface of the semiconductor element. The semiconductor element includes an electrode arranged on the upper surface of the semiconductor element. The semiconductor device includes via wirings and a wiring layer. The via wirings extend through the upper substrate in a thickness-wise direction and are connected to the electrode. The wiring layer is arranged on an upper surface of the upper substrate and is electrically connected to the electrode by the via wirings. The via wirings include two or more types of via wirings that differ from one another in planar size. The via wirings are arranged so that the planar size decreases from a peripheral portion of the semiconductor element toward a central portion of the semiconductor element in plan view.

Provided is a package having a component carrier with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and an optical chip and an electric chip being functionally coupled with each other and being embedded side-by-side in the component carrier so that a signal path between the optical chip and the electric chip is within a horizontal plane.