A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.

According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.

A printed circuit board includes: a first board unit including a plurality of first insulating layers and a plurality of first wiring layers respectively disposed on or in the plurality of first insulating layers; a second board unit including one or more second insulating layers and one or more second wiring layers respectively disposed on or in the one or more second insulating layers; and a first passive device embedded in at least one of the first and second board units. The second board unit is disposed on the first board unit, and the first board unit has a second cavity passing through at least a portion of the plurality of first insulating layers on the first passive device based on a stacking direction of the plurality of first wiring layers.

A power module (1) comprises a first switch (2) comprising a first switch element (9) and an associated first diode (10), a second switch (3) comprising a second switch element (11) and an associated second diode (12), the first and second switches (2, 3) being electrically connected to form a half-bridge, wherein the switch elements (9, 11) and diodes (10, 12) are located next to each other, wherein the second switch element (11) and second diode (12) are located between the first switch element (9) and the first diode (10).

According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.

According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

A light-emitting/receiving device including: a diode-type light-emitting element formed on a semiconductor substrate; a diode-type light-receiving element formed on the semiconductor substrate; a light source driving unit configured to supply a first common voltage to an anode or a cathode of the light-emitting element to drive the light-emitting element; and a light signal processing unit configured to perform current/voltage conversion on an output current outputted from the light-receiving element, by referring to a second common voltage.

In an electric circuit body, at least one of the cooling members fixed to both surfaces of a first semiconductor module and a second semiconductor module includes a first heat dissipation region that abuts on the first semiconductor module through a heat conduction member, a second heat dissipation region that abuts on the second semiconductor module through the heat conduction member, and a low rigidity portion formed between the first heat dissipation region and the second heat dissipation region to have lower rigidity the first heat dissipation region and the second heat dissipation region; and the fixing member fixes the cooling member to both surfaces of the first semiconductor module and the second semiconductor module in the low rigidity portion of the cooling member.