A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

A light emitting device includes: a base having a bottom face and a lateral part surrounding the bottom face and extending upwards from the bottom face, wherein the lateral part comprises a first stepped portion and a second stepped portion facing the first stepped portion; a first semiconductor laser element disposed on the bottom face and located between the first stepped portion and the second stepped portion in a top view, wherein the first semiconductor laser element is configured to emit light towards the second stepped portion; a first wiring region located on the first stepped portion; and one or more first wires, each having a first end that is connected to the first wiring region. At least one of the one or more first wires is electrically connected to the first semiconductor laser element.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

In an embodiment A package includes a casing having an opening and enclosing a cavity, a die accommodated in the cavity and a membrane attached to the casing, the membrane being air-permeable, covering and sealing the opening, wherein the membrane is configured to allow only a lateral gas flow, and wherein a blocking member is configured to block a vertical gas flow through the membrane into the cavity, the blocking member tightly covering a surface of the membrane at least in an area comprising the opening.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

A method of transferring a micro device and an array of micro devices are disclosed. A carrier substrate carrying a micro device connected to a bonding layer is heated to a temperature below a liquidus temperature of the bonding layer, and a transfer head is heated to a temperature above the liquidus temperature of the bonding layer. Upon contacting the micro device with the transfer head, the heat from the transfer head transfers into the bonding layer to at least partially melt the bonding layer. A voltage applied to the transfer head creates a grip force which picks up the micro device from the carrier substrate.

A method of transferring a micro device and an array of micro devices are disclosed. A carrier substrate carrying a micro device connected to a bonding layer is heated to a temperature below a liquidus temperature of the bonding layer, and a transfer head is heated to a temperature above the liquidus temperature of the bonding layer. Upon contacting the micro device with the transfer head, the heat from the transfer head transfers into the bonding layer to at least partially melt the bonding layer. A voltage applied to the transfer head creates a grip force which picks up the micro device from the carrier substrate.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level, where the second level overlays the first level and includes a plurality of second transistors; a fourth metal layer overlaying the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level and has a diameter of less than 500 nm and greater than 5 nm, where the third metal layer is connected to provide a power or ground signal to at least one of the second transistors.

A method for the transfer of components from a sender substrate to a receiver substrate includes provision and/or production of the components on the sender substrate, transfer of the components of the sender substrate to the transfer substrate, and transfer of the components from the transfer substrate to the receiver substrate.The components can be transferred selectively by means of bonding means and/or debonding means.

Method and arrangement for assembling one or more microchips (415; 615; 715; 815; 915; 1015) into one or more holes (422; 722), respectively, in a substrate surface (421; 721) of a separate receiving substrate (420; 720; 820; 1020). The holes (422; 722) of the substrate is for microchip insertion out-of-plane in relation to said substrate surface. Each of said microchips is provided with a ferromagnetic layer (213; 613) of ferromagnetic material. The microchips are placed (503) on said substrate surface (421; 721) and it is applied and moved (504) one or more magnetic fields affecting said ferromagnetic layer (213; 613) of each microchip such that the microchips thereby become out-of-plane oriented in relation to said substrate surface (421; 721) and move over the substrate surface (421; 721) until assembled into said holes (422; 722).