Patent classifications
H01L2924/1515
Semiconductor device package having continously formed tapered protrusions
The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate. A distance between the second surface of the substrate and an extension of the second surface of the semiconductor device on the first surface of the substrate is less than or equal to twice a distance between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate extends along at least three sides of the semiconductor device.
INTERCONNECTION BETWEEN CHIPS BY BRIDGE CHIP
A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.
Edge-notched substrate packaging and associated systems and methods
Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.
WELDING METHOD OF DEMETALLIZED CERAMIC SUBSTRATE HAVING SURFACE CAPILLARY MICROGROOVE STRUCTURE
The present invention discloses a welding method of a demetallized ceramic substrate having a surface capillary microgroove structure. The demetallized ceramic substrate includes a ceramic substrate main body and surface capillary microstructures. The surface capillary microstructures are arranged on two lateral sides of the ceramic substrate main body and the surface capillary microstructures specifically are capillary microgrooves. The welding method includes the following steps: fixing a chip to an upper surface of the demetallized ceramic substrate having the surface capillary microgroove structure, fixing the ceramic substrate with the chip to a printed circuit board having a bonding pad, and placing melted solder on the bonding pad, and driving the solder to ascend to an electrode of the chip from the bonding pad in a lower layer by means of a capillary force, thereby realizing an electrical connection between the chip and the printed circuit board.
Bonding apparatus
A bonding apparatus includes a bonding stage on which either a rectangular substrate or a circular substrate can be installed; a first transport mechanism which transports the rectangular substrate from a first carry-in unit to the bonding stage and from the bonding stage to a first carry-out unit; and a second transport mechanism which transports the circular substrate from a second carry-in/out unit to the bonding stage and from the bonding stage to the second carry-in/out unit, in which a first transport path determined by the first transport mechanism and a second transport path determined by the second transport mechanism partially overlap.
Bonding apparatus
A bonding apparatus includes a bonding stage on which either a rectangular substrate or a circular substrate can be installed; a first transport mechanism which transports the rectangular substrate from a first carry-in unit to the bonding stage and from the bonding stage to a first carry-out unit; and a second transport mechanism which transports the circular substrate from a second carry-in/out unit to the bonding stage and from the bonding stage to the second carry-in/out unit, in which a first transport path determined by the first transport mechanism and a second transport path determined by the second transport mechanism partially overlap.
SEMICONDUCTOR DEVICE
The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
EDGE-NOTCHED SUBSTRATE PACKAGING AND ASSOCIATED SYSTEMS AND METHODS
Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.
Electronic circuit connection method and electronic circuit
The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.
SUBSTRATE COMPRISING INTERCONNECTS EMBEDDED IN A SOLDER RESIST LAYER
A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.