An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.

A substrate for mounting a semiconductor element thereon has columnar terminal portions formed by concavities provided on an upper surface of a metal plate made of a copper-based material, and is provided with a roughened silver plating layer having acicular projections, applied, as the outermost plating layer, to top faces of the columnar terminal portions. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon facilitates thin design of semiconductor packages produced by flip-chip mounting, can be manufactured with improved productivity owing to reduction in cost and operation time, achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

A device structure comprises a patterned substrate comprising a substrate surface and a substrate post protruding from the substrate surface. The substrate post comprises a substrate post material. A component has a component top side and a component bottom side opposite the component top side. The component bottom side is disposed on the substrate post and extends over at least one edge of the substrate post. The component comprises a component material different from the substrate post material and the component comprises a broken (e.g., fractured) or separated component tether.

A substrate for mounting a semiconductor element thereon has columnar terminal portions formed by concavities provided on an upper surface of a metal plate made of a copper-based material, and is provided with a roughened silver plating layer having acicular projections, applied, as the outermost plating layer, to top faces of the columnar terminal portions. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon facilitates thin design of semiconductor packages produced by flip-chip mounting, can be manufactured with improved productivity owing to reduction in cost and operation time, achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A bonding apparatus includes a bonding stage on which either a rectangular substrate or a circular substrate can be installed; a first transport mechanism which transports the rectangular substrate from a first carry-in unit to the bonding stage and from the bonding stage to a first carry-out unit; and a second transport mechanism which transports the circular substrate from a second carry-in/out unit to the bonding stage and from the bonding stage to the second carry-in/out unit, in which a first transport path determined by the first transport mechanism and a second transport path determined by the second transport mechanism partially overlap.

A bonding apparatus includes a bonding stage on which either a rectangular substrate or a circular substrate can be installed; a first transport mechanism which transports the rectangular substrate from a first carry-in unit to the bonding stage and from the bonding stage to a first carry-out unit; and a second transport mechanism which transports the circular substrate from a second carry-in/out unit to the bonding stage and from the bonding stage to the second carry-in/out unit, in which a first transport path determined by the first transport mechanism and a second transport path determined by the second transport mechanism partially overlap.

Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.

A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first insulation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.