In a described example, an apparatus includes: a multilayer package substrate including a die mount area on a die side surface and comprising power pads and ground pads on an opposing board side surface, the multilayer package substrate including post connect locations on the die side surface for receiving power post connects and for receiving ground post connects for a flip chip mounted semiconductor device, the power post connect locations and the ground post connect locations positioned in the die mount area, the power post connect locations and the ground post connect locations intermixed in the die mount area; and a semiconductor device having post connects extending from bond pads on a device side surface of the semiconductor device mounted to the die side surface of the multilayer package substrate by solder joints between the post connects and the post connect locations.

Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.

Provided are a power module and a manufacturing method thereof. The power module includes an insulating substrate, a first, a second and a third conductive layers, a first thermal interface material layer, a first and a second chips and a thermal conductive layer. The insulating substrate has a first and a second surfaces opposite to each other. The first and the second conductive layers are disposed on the first surface, and electrically separated from each other. The first thermal interface material layer is disposed on the first conductive layer. The third conductive layer is disposed on the first thermal interface material layer. The first chip is disposed on the third conductive layer and electrically connected to the third conductive layer. The second chip is disposed on the second conductive layer and electrically connected to the second conductive layer. The thermal conductive layer is disposed on the second surface.

An integrated device package is disclosed. The integrated device package can include a carrier that has an opening extending at least partially through a thickness of the carrier. The integrated device package can include a microelectronicmechanical systems die that is at least partially disposed in the opening and mechanically and electrically coupled to the carrier. The integrated device package can include a lid that is coupled to the carrier. The lid and the microelectronicmechanical systems die are spaced by a gap defining a back volume.

An integrated device package is disclosed. The integrated device package can include a printed circuit board and a microelectronicmechanical systems die that is at least partially disposed within the printed circuit board and electrically coupled to the printed circuit board. The integrated device package can include a filler material that is at least partially disposed between the microelectronicmechanical systems die and the printed circuit board. The integrated device package can include a lid that is coupled to the printed circuit board. The lid and the microelectronicmechanical systems die are spaced by a gap defining a back volume.

An integrated device package is disclosed. The integrated device package can include a carrier that has a multilayer structure having a first layer and a second layer. The first layer at least partially defines a lower side of the carrier. An electrical resistance of the second layer is greater than an electrical resistance of the first layer. The integrated device package can include a microelectronicmechanical systems die that is mounted on an upper side of the carrier opposite the lower side. The integrated device package can include a lid that is coupled to the carrier. The lid and the microelectronicmechanical systems die are spaced by a gap defining a back volume.

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

The present invention relates to a chip-on film type semiconductor package including an integrated circuit chip, a printed circuit board layer, an outer lead bonder pad, and a graphite layer, in which the integrated circuit chip is connected to one surface of the printed circuit board layer directly or by means of a mounting element, the outer lead bonder pad is located on one surface of the printed circuit board layer, and the graphite layer is laminated on an opposite surface of the printed circuit board layer and a display device including the same.

Provided is a heat sink having a clad structure of Co—Mo composite materials and Cu materials, satisfying high heat-sink properties required of the heat sink for use in a semiconductor package with a frame on which a high-output and small-sized semiconductor is mounted, and preventing, when applied to the semiconductor package with a frame, crack of the frame due to local stress concentration. The heat sink has three or more Cu layers and two or more Cu—Mo composite layers alternately stacked in a thickness direction so that the Cu layers are outermost layers on both sides thereof, the Cu layers as the outermost layers each having a thickness t.sub.1 of 40 μm or more, the heat sink satisfying 0.06≤t.sub.1/T≤0.27 (where T: heat sink thickness) and t.sub.2/T≤0.36/[(total number of layers−1)/2] (where t.sub.2: Cu—Mo composite layer thickness, the total number of layers: sum of numbers of Cu layers and Cu—Mo composite layers).

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.