A package includes: a vertically extending first electronic component with at least one exposed electrically conductive first terminal; a vertically extending second electronic component with at least one exposed electrically conductive second terminal; and a clip with an accommodation volume in which the first electronic component and the second electronic component are accommodated and are held together. The at least one first terminal and the at least one second terminal are electrically accessible at a bottom of the clip.

Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

In a connection system for electronic components (1) comprising a plurality of insulating layers (2) and conductive layers (3) and further comprising at least one embedded electronic component (4) embedded within at least one of the plurality of insulating layers (2) and conductive layers (3) the at least one embedded electronic component (4) is at least one first transistor having a bulk terminal thereof in thermal contact with a thermal duct (6) comprised of a plurality of vias (7) reaching through at least one of an insulating layer (2) and a conductive layer (3) of the connection system for electronic components (1) and emerging on a first outer surface (8) of the connection system for electronic components (1) under a first surface-mounted component (10).

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

A method of producing a power semiconductor module includes providing a power electronics carrier that includes a structured metallization layer disposed on an electrically insulating substrate layer, performing a production step of the power semiconductor module using the power electronics carrier, using a sensor to obtain crack information during the production step, the crack information comprising information about whether one or more cracks occurred in the electrically insulating substrate layer during the production step, analyzing the crack information, and performing one or more of the following after analyzing the crack information: performing a subsequent production step of the power semiconductor module dependent upon the analyzed crack information, cataloging the analyzed crack information, and performing a further investigative step to inspect the electrically insulating substrate layer using the analyzed crack information.