A method of fabricating a semiconductor structure includes providing a first substrate comprising a first side and a second side opposite to the first side. A package is attached to the first side of the first substrate. A second substrate is attached to the second side of the first substrate. A plurality of electrical connectors is bonded between the second side of the first substrate and the second substrate. A lid is attached to the first substrate and the second substrate. The lid includes a ring part and a plurality of overhang parts. The ring part is over the first side of the first substrate. The plurality of overhang parts extends from corner sidewalls of the ring part toward the second substrate. The plurality of overhang parts are laterally aside the plurality of electrical connectors.

A power semiconductor module includes: a substrate with a metallization layer attached to a dielectric insulation layer and a semiconductor body mounted to the metallization layer; a housing at least partly enclosing the substrate and having sidewalls and a cover that at least partly covers an opening formed by the sidewalls and has a flexible portion; and a press-on pin having arranged on the substrate or semiconductor body. A first end of the press-on pin faces the substrate or semiconductor body and extends towards the cover such that a second end of the press-on pin contacts the flexible portion of the cover. The substrate in an area vertically below the press-on pin has a first spring constant k.sub.1 in a vertical direction that is perpendicular to a top surface of the substrate. The flexible portion of the cover has a second spring constant k.sub.2, where 0.5*k.sub.1≤k.sub.2≤5*k.sub.1.

According to various aspects, exemplary embodiments are disclosed of board level shields with virtual grounding capability. In an exemplary embodiment, a board level shield includes one or more resonators configured to be operable for virtually connecting the board level shield to a ground plane or a shielding surface. Also disclosed are exemplary embodiments of methods relating to making board level shields having virtual grounding capability. Additionally, exemplary embodiments are disclosed of methods relating to providing shielding for one or more components on a substrate by using a board level shield having virtual grounding capability. Further exemplary embodiments are disclosed of methods relating to making system in package (SiP) or system on chip (SoC) shielded modules and methods relating to providing shielding for one or more components of SiP or SoC module.

An electronic apparatus that includes a semiconductor device; an electronic packaging substrate for receiving the semiconductor device; a thermal interface material on the semiconductor device; and a lid in contact with the thermal interface material and having a zone of targeted flexibility spaced from the semiconductor device.

An electronic apparatus that includes a semiconductor device; an electronic packaging substrate for receiving the semiconductor device; a thermal interface material on the semiconductor device; and a lid in contact with the thermal interface material and having a zone of targeted flexibility spaced from the semiconductor device.

An electronic integrated circuit (IC) component is mounted to a substrate. A cap member is applied onto the substrate and covers the electronic IC component. The cap member includes an outer wall defining an opening and an inner wall surrounding the electronic IC component. The inner wall extends from a proximal end at the substrate towards a distal end facing the opening in the outer wall to provide a reception chamber for the electronic IC component and a peripheral chamber between the inner wall and the outer wall of the cap member. An encapsulant material is provided in the reception chamber to seal the electronic IC component without being present in the peripheral chamber.

A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed.

A method includes: providing a package body including a mounting part having a chip mounting region for mounting a semiconductor chip, a side wall part having a first sealing surface continuously provided over an entire perimeter of the mounting part, surrounding the chip mounting region and provided on the mounting part, a first recess provided on the first sealing surface, and a first solder outflow prevention part continuously provided on the first sealing surface and positioned closer to the chip mounting region side than the first recess; providing a cap having a second sealing surface facing the first sealing surface; providing a ball solder made of an alloy of gold and tin as principal ingredients; placing the ball solder in the first recess; placing the cap on the ball solder; and melting once and then solidifying the ball solder to bond the first sealing surface and the second sealing surface.

A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.