A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.

An electronic package and a heat dissipation structure thereof are provided, in which supporting members of the heat dissipation structure are arranged in edge areas, and no supporting member is arranged in corner areas. In this way, the supporting members are interrupted at the corner areas, so that stress can be prevented from concentrating in the corner areas, and the entire electronic package can be prevented from warping and delamination.

A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.

The present disclosure relates to non-planar inductive electrical elements in semiconductor package lead frames. A non-planar inductive element is formed from a lead frame in a semiconductor package. The semiconductor package also includes at least one semiconductor die coupled to the lead frame. The non-planar inductive element could be formed by deforming portions of a patterned planar lead frame blank to form the non-planar inductive element in a deformed lead frame blank. The deformed lead frame blank and the at least one semiconductor die could then be packaged into a semiconductor package. A setting tool could be used to deform the lead frame blank. A configurable lead frame blank could be configurable into any of a variety of inductive elements, through interconnection of lead frame segments using wire bonds, for example.

The present disclosure is directed to a patterned stiffener that includes a metallic body, which is a component of and is attached to a semiconductor device platform for providing rigidity. In an aspect, there are patterned sections formed on the metallic body that act to modulate the metallic body to obtain a desired configuration for the semiconductor device platform. In another aspect, the present disclosure is also directed to a method that includes providing a platform for forming an electronic component, disposing a stiffener having a metallic body on the platform, disposing at least one semiconductor device onto the platform, performing one or more bonding process steps, and exposing the stiffener to localized heating to modulate changes in the stiffener to a pre-determined shape or desired configuration.

A strip-shaped substrate made from a film includes a plurality of units for producing chip carriers. Each unit has a chip island for fixing a semiconductor chip, electrodes for electrical connection of the semiconductor chip, and through-openings for structuring the unit. At least one through-opening forms an anchoring edge for a casting compound for encapsulating the semiconductor chip. A surface section of the film abutting the through-opening is chamfered to form the anchoring edge. The anchoring edge protrudes past the side of the film on which the chip island is arranged.

A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Semiconductor device packages are provided. In one example, the semiconductor device package includes a semiconductor die. The semiconductor die includes a wide bandgap semiconductor material. The semiconductor die includes a metallization layer on a surface of the semiconductor die. The semiconductor device package includes a submount. The metallization of the semiconductor die is directly bonded to the submount.

There are provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where a connection section used for the connection to a semiconductor element is arranged and a manufacturing method for a semiconductor module. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have through holes where sealing resins are formed, the sealing resins connecting adjacent housing sections and the sealing resin formed in the through hole being continuous with the sealing resins formed in the housing sections.

A semiconductor device, including: a semiconductor chip including a main electrode on a front surface thereof; a first conductive plate having a first main surface with a chip area defined thereon, a rear surface of the semiconductor chip being bonded to the chip area; a second conductive plate provided adjacent to the first conductive plate in a plan view of the semiconductor device; a supporting part provided adjacent to the first conductive plate in the plan view, and insulated from the first conductive plate, the supporting part and the second conductive plate being on two opposite sides of the chip area; and a lead frame, which including a first bonding part bonded to the supporting part, a second bonding part bonded to the second conductive plate, and an electrode bonding part bonded to the main electrode of the semiconductor chip via a bonding member.