A chip protection device includes a protection frame extending around side surfaces of a semiconductor chip mounted on a substrate. The protection frame includes a plurality of side walls, each wall facing and spaced apart from a respective side surface of the semiconductor chip, and a plurality of upper walls, each upper wall extending inward from an upper portion of a respective side wall toward the semiconductor chip. A plurality of apertures are formed through the side walls and through which a fluid enters and exits. The protection frame defines an inner space in which the fluid can flow via the plurality of apertures. Heat from the side surfaces of the semiconductor chip is transferred to the fluid in the inner space.

An electronic device package includes a frame, an electronic device mounted to the frame, surface-mount leads, and a gel at least partially filling a cavity between the electronic device and the frame. The electronic device includes electronic circuitry provided on an electronic device substrate, and the surface-mount leads are electrically connected to the electronic circuitry and extend laterally and outwardly from an outer perimeter of the frame. The gel in the cavity covers the electronic circuitry.

A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature. Furthermore, additional stress can be enhanced by means of different embodiments involving the support, such as ring or multi-layer frame.

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole.

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole.

A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip.

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.

An electronic package and a manufacturing method thereof are provided, in which a dam is surrounding an electronic component on a carrier structure, the electronic component is encapsulated by a thermal conduction layer, and the electronic component, the dam and the thermal conduction layer are covered by a heat sink, such that the dam strongly supports the heat sink to effectively disperse the thermal stress, so as to effectively control the warpage of the heat sink to prevent the problem of delamination from occurring between the heat sink and the thermal conduction layer.

A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

An electronic package and a heat dissipation structure thereof are provided, in which supporting members of the heat dissipation structure are arranged in edge areas, and no supporting member is arranged in corner areas. In this way, the supporting members are interrupted at the corner areas, so that stress can be prevented from concentrating in the corner areas, and the entire electronic package can be prevented from warping and delamination.