A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

A semiconductor package includes an interposer; a first stacked chip including a first semiconductor chip disposed on the interposer and one or more second semiconductor chips disposed on the first semiconductor chip; a first molding layer surrounding the first stacked chip; and a second molding layer surrounding the first molding layer, wherein the second molding layer extends from an uppermost surface of the interposer to a trench of the interposer.

A package that includes a substrate, an integrated device, a first encapsulation layer and a void. The substrate includes a first surface. The integrated device is coupled to the first surface of the substrate. The first encapsulation layer is located over the first surface of the substrate and the integrated device. The first encapsulation layer includes an undercut relative to a side surface of the integrated device. The void is located between the integrated device and the first surface of the substrate. The void is laterally surrounded by the undercut of the encapsulation layer.

A semiconductor structure includes a first substrate including a first pad thereover, a second substrate including a bump thereover and a dielectric material. The first pad includes an inner portion and an outer portion being higher than and surrounding the inner portion. The bump is bonded to the inner portion and surrounded by the outer portion. The dielectric material is disposed between the first substrate and the second substrate to encapsulate the first pad and the bump.

A semiconductor package includes a first interconnection structure, a first semiconductor chip on the first interconnection structure, an encapsulant covering the first semiconductor chip, a second interconnection structure disposed on the first semiconductor chip and the encapsulant, including a plurality of interconnection layers, and having an opening having a step portion, exposing a portion of an upper surface of at least one of the plurality of interconnection layers, and a heat dissipation pattern disposed in the opening, passing through the encapsulant and in contact with at least a portion of an upper surface of the first semiconductor chip, and including a material having a thermal conductivity higher than thermal conductivity of silicon (Si). The heat dissipation pattern includes a lower portion having a first width, and an upper portion disposed on the lower portion and having a second width greater than the first width, and the upper portion of the heat dissipation pattern is in contact with the exposed portion of the upper surface of the at least one interconnection layer.

A semiconductor device, including a substrate having a mounting area on a front surface thereof, a semiconductor chip disposed in the mounting area, and an exterior member having a bottom surface bonded to the front surface of the substrate, the exterior member continuously surrounding the mounting area in a loop shape in a plan view of the semiconductor device, to thereby enclose a housing space, the mounting area being in the housing space. The semiconductor device further includes a sealing material sealing the housing space.

A POP structure includes a first package structure, an interposer, and a second package structure. The first package structure includes a first carrier, a first chip, conductive structures, and a first insulation encapsulation. The first carrier has a first surface and a second surface opposite to the first surface. The first chip and the conductive structures are disposed on the first surface of the first carrier. The first insulation encapsulation is formed on the first surface of the first carrier and encapsulates the conductive structures and the first chip. Top surfaces of the conductive structures are exposed through the first insulation encapsulation and are coplanar. The interposer is disposed on and electrically connected to the first package structure. The second package structure is disposed on and electrically connected to the interposer. A manufacturing method of a POP structure is also provided.

A temporary protective film for semiconductor encapsulation molding includes a support film and an adhesive layer. The adhesive layer contains a thermoplastic resin and at least one compound selected from the group consisting of sorbitol polyglycidyl ether, polyethylene glycol diglycidyl ether, a glycidyl ether of an aliphatic alcohol having 10 to 20 carbon atoms, glycerol polyglycidyl ether, a polyalkylene glycol ester of a fatty acid having 2 to 30 carbon atoms, a dipentaerythritol ester of a fatty acid having 2 to 20 carbon atoms, polyethylene glycol monoalkyl ether, and polyethylene glycol dialkyl ether.

A semiconductor device includes a substrate, a conductive portion, a sealing resin, a plurality of semiconductor chips, and a plurality of temperature detection elements. The substrate has a substrate obverse surface and a substrate reverse surface that face opposite sides in a thickness direction. The conductive portion is formed on the substrate obverse surface. The sealing resin covers at least a part of the substrate. The sealing resin also covers the entire conductive portion. The plurality of semiconductor chips are disposed on the substrate obverse surface. The plurality of temperature detection elements are disposed on the substrate obverse surface. The number of temperature detection elements is equal to or greater than the number of semiconductor chips.

A power semiconductor module includes: a substrate with a metallization layer attached to a dielectric insulation layer and a semiconductor body mounted to the metallization layer; a housing at least partly enclosing the substrate and having sidewalls and a cover that at least partly covers an opening formed by the sidewalls and has a flexible portion; and a press-on pin having arranged on the substrate or semiconductor body. A first end of the press-on pin faces the substrate or semiconductor body and extends towards the cover such that a second end of the press-on pin contacts the flexible portion of the cover. The substrate in an area vertically below the press-on pin has a first spring constant k.sub.1 in a vertical direction that is perpendicular to a top surface of the substrate. The flexible portion of the cover has a second spring constant k.sub.2, where 0.5*k.sub.1≤k.sub.2≤5*k.sub.1.