At least some embodiments of the present disclosure relate to a wearable device. The wearable device comprises a substrate, a detecting module disposed on the substrate, and a control module disposed on the substrate. The control module is electrically connected to the detecting module. The control module is configured to receive a signal from the detecting module and to control the wearable device in response to the signal.

An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space.

A package substrate includes a metallic lead frame that includes first frame portions in a lattice shape along planned dividing lines and a plurality of first electrode portions extending from each of the first frame portions, a connection frame that includes second frame portions in a lattice shape along the planned dividing lines and a plurality of second electrode portions extending from each of the second frame portions, the connection frame being superposed on a side of the lead frame on which a device chip is disposed, and a mold resin that covers the device chip and the connection frame. Distal ends of the second electrode portions are formed in a protruding shape and connected to the first electrode portions, and the connection frame forms an electrode when electroplating processing is applied to sections of the first electrode portions.

A package structure includes a core substrate including a substrate base including a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities; and a plurality of bridge structures that extend between each of the plurality of blocks and the substrate base, a plurality of semiconductor chips in the plurality of first cavities, and a molding layer configured to cover the core substrate and the plurality of semiconductor chips, a portion of the molding layer being in the plurality of first cavities and the plurality of second cavities.

A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

An electronic device includes a substrate, a first plate having a first internal surface facing a first surface of the substrate, and at least one first through-hole and at least one second through-hole, first and second semiconductor packages spaced apart from each other between the first surface and the first internal surface, a first thermal interface material layer contacting an upper surface of the first semiconductor package and the first internal surface, and filling at least a portion of the at least one first through-hole, and a second thermal interface material layer contacting an upper surface of the second semiconductor package and the first internal surface, and filling at least a portion of the at least one second through-hole. At least one of side surfaces of the first and second thermal interface material layers is exposed to an empty space between the first internal surface and the first surface.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.