An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.

A method for manufacturing a light emitting device includes: preparing a first substrate having an upper surface comprising an element placement region; placing a light emitting element in the element placement region; disposing an uncured, sheet-like light-transmissive member on the light emitting element and bringing an outer edge of a lower surface of the light-transmissive member into contact with an outer upper surface of the element placement region of the first substrate by pressing the light-transmissive member; and disposing a first protrusion portion along an outer edge of an upper surface of the light-transmissive member so that the first protrusion portion extends over the upper surface of the first substrate and the upper surface of the light-transmissive member.

A semiconductor device is vertically mounted on a medium such as a printed circuit board (PCB). The semiconductor device comprises a block of semiconductor dies, mounted in a vertical stack without offset. Once formed and encapsulated, side grooves may be formed in the device exposing electrical conductors of each die within the device. The electrical conductors exposed in the grooves mount to electrical contacts on the medium to electrically couple the semiconductor device to the medium.

A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a first molding layer on the package substrate and surrounding the first semiconductor chip, a redistribution layer on the first molding layer, a first through via that vertically penetrates the first molding layer and connects the package substrate to the redistribution layer, a second semiconductor chip mounted on the redistribution layer, a second molding layer on the redistribution layer and surrounding the second semiconductor chip, and a second through via that vertically penetrates the second molding layer and is connected to the redistribution layer. A first width of the first through via is less than a second width of the second through via. The second through via is electrically floated from a signal circuit of the second semiconductor chip.

A semiconductor device according to the present embodiment includes a substrate and a semiconductor chip. The substrate has a first face and a plurality of conductive connection parts provided on the first face. The semiconductor chip has a second face that faces the first face and a plurality of connection bumps provided on the second face and electrically connected to the plurality of conductive connection parts. The conductive connection part arranged in a chip outer peripheral region of a chip region on the first face where the semiconductor chip is arranged is different in thickness from the conductive connection part arranged in a chip central region of the chip region.

A semiconductor package includes a substrate, an interposer, a primary component layer, a first redistribution layer, multiple solder bumps and a first hybrid bonding structure. The interposer is disposed above the substrate and includes multiple TSV sets. The primary component layer is disposed above the interposer and includes multiple first chips and a first molding material that fills the space between the multiple first chips. The first redistribution layer is disposed between the primary component layer and the interposer and includes at least one portion of an antenna structure. The plurality of solder bumps is disposed between the substrate and the interposer. The first hybrid bonding structure is disposed between the multiple first chips and the multiple TSV sets for electrical connection in between and includes multiple connection components that respectively apply bonding of multiple metal pieces in between.

A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

A packaged power semiconductor device includes a power semiconductor wafer, a heat conduction layer, and a heat sink that are sequentially stacked, and a sealing part configured to wrap and seal the power semiconductor wafer and at least part of the heat conduction layer. The packaged power semiconductor device further includes a pin, where the pin includes a connection segment wrapped inside the sealing part, and an extension segment located outside the sealing part. The connection segment is electrically connected to the power semiconductor wafer, and a shortest distance between the extension segment and a first outer surface is greater than a creepage distance corresponding to a highest working voltage of the power semiconductor wafer. This can avoid a creepage phenomenon of the pin by limiting a distance between the first outer surface and the extension segment that is of the pin and that is exposed outside the sealing part.

A method includes placing a package, which includes a first package component, a second package component, and an encapsulant encapsulating the first package component and the second package component therein. The method further includes attaching a first thermal interface material over the first package component, attaching a second thermal interface material different from the first thermal interface material over the second package component, and attaching a heat sink over both of the first thermal interface material and the second thermal interface material.