A semiconductor device, including a substrate having a mounting area on a front surface thereof, a semiconductor chip disposed in the mounting area, and an exterior member having a bottom surface bonded to the front surface of the substrate, the exterior member continuously surrounding the mounting area in a loop shape in a plan view of the semiconductor device, to thereby enclose a housing space, the mounting area being in the housing space. The semiconductor device further includes a sealing material sealing the housing space.

An underfill film material and a method for manufacturing a semiconductor device using the same which enables voidless mounting and favorable solder bonding properties are provided. An underfill material is used which contains an epoxy resin, an acid anhydride, an acrylic resin and an organic peroxide, the underfill material exhibits non-Bingham fluidity at a temperature ranging from 60° C. to 100° C., a storage modulus G′ measured by dynamic viscosity measurement has an inflection point in an angular frequency region below 10E+02 rad/s, and the storage modulus G′ in the angular frequency below the inflection point is 10E+05 Pa or more and 10E+06 Pa or less. This enables voidless packaging and excellent solder connection properties.

A power module includes a first conductor plate to which a first power semiconductor element is bonded, a second conductor plate to which a second power semiconductor element is bonded, the second conductor plate being disposed adjacent to the first conductor plate, a first heat-dissipating member disposed counter to the first conductor plate and the second conductor plate, and a first insulating sheet member disposed between the first heat-dissipating member and the first conductor plate. The first power semiconductor element is disposed at a position at which a first length from an end of the first conductor plate, the end being closer to the second conductor plate, to the first power semiconductor element is larger than a second length from an end of the first conductor plate, the end being far from the second conductor plate, to the first power semiconductor element, and the second length is larger than the thickness of the first conductor plate.

In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

A light emitting device includes a light emitting element, a molded member, and a sealing member. The light emitting element is arranged on or above the molded member. The sealing member covers the light emitting element. The sealing member contains a phosphor, and a filler material. The phosphor can be excited by light of the light emitting element, and emit luminescent radiation. The filler material contains neodymium hydroxide, neodymium aluminate or neodymium silicate. The filler material absorbs a part of the spectrum of the mixed light of the light emitting element and the phosphor so that the other parts of the spectrum of this mixed light are extracted from the light emitting device.

A temporary protective film for semiconductor encapsulation molding includes a support film and an adhesive layer. The adhesive layer contains a thermoplastic resin and at least one compound selected from the group consisting of sorbitol polyglycidyl ether, polyethylene glycol diglycidyl ether, a glycidyl ether of an aliphatic alcohol having 10 to 20 carbon atoms, glycerol polyglycidyl ether, a polyalkylene glycol ester of a fatty acid having 2 to 30 carbon atoms, a dipentaerythritol ester of a fatty acid having 2 to 20 carbon atoms, polyethylene glycol monoalkyl ether, and polyethylene glycol dialkyl ether.

Provided is an encapsulation method not causing molding failures such as filling failures and flow marks when collectively encapsulating a large-area silicon wafer or substrate with a resin composition. Specifically, provided is a method for encapsulating a semiconductor element-mounted base material, using a curable epoxy resin composition containing: an epoxy resin (A), a curing agent (B), a pre-gelatinizing agent (C) and a filler (D). The semiconductor element-mounted base material is collectively encapsulated under conditions of (a) molding method: compression molding, (b) molding temperature: 100 to 175° C., (c) molding period: 2 to 20 min and (d) molding pressure: 50 to 350 kN.

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.

A semiconductor device includes a lead frame having a first principal surface which includes a recess, and a second principal surface opposite to the first principal surface, a relay board, disposed in the recess, and having a third principal surface, and a fourth principal surface opposite to the third principal surface, wherein the fourth principal surface opposes a bottom surface of the recess, a first semiconductor chip disposed on the third principal surface, a first conductive material connecting the lead frame and the relay board, and a second conductive material connecting the relay board and the first semiconductor chip. A distance between the second principal surface and the third principal surface is less than or equal to a distance between the second principal surface and the first principal surface.